Design example Binary Multiplier Block diagram ASM chart

Design example Binary Multiplier

Block diagram

ASM chart

Numerical example

Control logic

Control block • L is required for loading the sum into register A if Q 0=1 while in state T 2

State assignment

State table for control circuit

Logic diagram of control

One F. F. per state

HDL description HDL Example 8 -5 module mltp(S, CLK, Clr, Binput. Qinput, C, A, Q, P) ; input S, CLK, Cir; input [4: 01 Binput. Qinput; //Data inputs output C; output [4: 0] A, Q; output [2: 0] P; reg C; reg [4: 0] A, Q, B; reg [2: 0] P; reg [1: 0] pstate, nstate; //control register parameter T 0=2'b 00, Tl=2'b 01, T 2=2'bl 0, T 3=2'bll; wire Z; assign Z = ~|P; //Check for zero always @(negedge CLK or negedgo Cir) if (~Clr) pstate = T 0; else pstate <= nstate; always @(S or Z or pstate) case (pstate) T 0: if (S) nstate = Tl; else nstate = T 0; Tl: nstate = T 2; T 2: nstate = T 3 ; T 3: if (Z) nstate = TO; else nstate = T 2; endcase

always @(negedge CLK) case (pstate) TO: B <= Binput; //Input multiplicand Tl: begin A <= 5'b 00000; C <= 1'b 0; P <= 3~b 101; //Initialize counter to n=5 Q <= Qinput; //Input multiplier end T 2: begin P <= P - 3'b. OOl; //Decrement counter if (Q[0]) {C, A} <= A + B; //Add multiplicand end T 3: begin C <= 1'b 0; //Clear C A <= {C, A[4: 1]}; //Shift right A Q <= {A[0], Q[4: l]}; //Shift right Q endcase endnodule

HDL Example 8 -6 Test bench module test_mltp; reg S, CLK, Clr; reg [4: 0] Binput, Qinput; wire C; wire [4: 0] A, Q; wire [2: 0] P; mitp mp(S, CLK, Clr, Binput, Qinput, C, A, Q, P), initi. Al begin S=0; CLK=0; Clr=0; #5 S=l; Clr=l; Binput = 5'b 10111; Qinput = 5'b 10011; #15 S = 0; end initial begin repeat (26) #5 CLK = ~CLK; end always @(negedge CLK) $strobe("C=%b A=%b Q=%b P=%b time=%0 d", C, A, Q, P, $time) endmodule