Current Flattening in Software and Hardware for Security

Current Flattening in Software and Hardware for Security Applications Authors: R. Muresan, C. Gebotys Presentation By: Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 1

Outline o o Introduction Power analysis attacks (PAAs) n o Current flattening technique n n o Definitions, examples, countermeasures Definition, methodology, implementations Current flattening as a countermeasure against PAAs Results and conclusions Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 2

Introduction o o o Embedded systems are increasingly used in security applications The software and the hardware components must be secure against all threats Current flattening is a potential countermeasure against PAAs Radu Muresan Plaintext Encryption Ciphertext Message Channel ke Decryption Key Channel Plaintext kd Key Generation Secret-key Cryptosystem: ke = kd Public – key Cryptosystem: ke ≠ kd CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 3

What is a Power Analysis Attack ? o Side-channel attacks exploit correlation between secret parameters and variations in timing, power consumption, and other emanations from cryptographic devices to reveal secret keys Radu Muresan Power Supply Current or Power Measurement R Attacker’s Point Cryptographic Device CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 4

Example, DPA Attack on a Scalar Multiplication Algorithm for EC Protocols o o DPA, uses correlation between power consumption and specific key-dependent bits k. P, scalar multiplication n o o o k. P 1, k. P 2, . . . , k. Pn => Ci(t) = power kn-1 = 1; After the first iteration => Q[0] = 2 Pi Second iteration n n o Double-and-add approach, binary k(2) = (kn-1, . . . , k 0) If kn-2=1 => Q[1] = 4 P If kn-2=0 => Q[1] = 5 P g(t)=<Ci(t)>i=1, . . . , k|si=1 - <Ci(t)>i=1, . . . , k|si=0 Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 5

Example, DPA Attack on a Scalar Multiplication Algorithm for EC Protocols Simulated correlation function between the points 4 Pi and power consumption Ci(t) when kn-2 = 0. o o A peak is observed when 4 Pi are computed by the card No peak is observed when 4 Pi are never computed by the card Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 6

Countermeasures Against PAAs o Against timing attacks n o Against simple power analysis attacks n o Avoiding; Creating; Symmetric Against differential power analysis attacks n n o Equalizing; Randomizing; Blinding Randomization; Blinding Hardware: non-deterministic techniques Against all PAAs n Radu Muresan Proposed: current flattening technique CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 7

What is Current Flattening? o Current flattening targets a flat (emission free) current consumption measured at an attacker’s point of a cryptographic device Radu Muresan Attacker’s Point Current Flattening (internal) External Current Filtering Devices Cryptographic Device CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 8

Behind Current Flattening o Current consumption in a processor is a function of: n n The hardware architecture The instruction type The instruction sequencing Data manipulated Examples of current dynamics Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 9

Software Method o Program execution is composed of two types of cycles n o charging; discharging Code transformations are generated for classes of instructions Example Class FLATTEN 0 [ALU Units] FLATTENi [ALU Units] ALU 1 1 NOP 0 0 CONTRO L 4 3 Radu Muresan Current measurements used for determining code transformations CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 10

Hardware Method o Pipeline current flattening module Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 11

Hardware Method o Feedback current module Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 12

Does Current Flattening Protect Against PAAs? o o Software method does not support DPA due to the fact that the program to data dependencies are not covered Hardware method has potential to cover all PAAs n n Radu Muresan Supports real-time current adjustment at the clock frequency Covers both current to data and to instruction dependencies CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 13

Results of Software Flattening o The experiments used the polymul. NIST. asm implementation of an EC scalar multiplication (k. P), where: n n o P a fixed point on a known elliptic curve k a secret key Target processor: Motorola SC 140 DSP Radu Muresan Real current measurements CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 14

Results of Software Flattening o o o Pk-Pk current variation reduced by 70 to 78% Energy consumption increased by 71 to 74% Execution time increased by up to 135% Radu Muresan Version Start Time [μs] End Time [μs] Energy Prog. [μJ] Mean [m. A] M 1 25 681 209. 9 0. 168 18. 85 67. 7 M 2 25 1569 363. 2 0. 124 1. 60 20. 3 M 4 25 1545 359. 9 0. 125 1. 91 16. 8 M 7 25 1569 365. 5 0. 125 1. 98 14. 3 S [m. A] Pk-Pk [m. A] Data analysis for software flattening CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 15

Results of Hardware Flattening o Instantaneous current simulation for polymul. asm n n o polymul. asm is a subroutine of polymul. NIST. asm polymul. asm is a target of PAAs Target system n Radu Muresan Motorola SC 140 DSP plus the Feedback Current Module Current simulation and real current measurement CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 16

Results of Hardware Flattening o o o Pk-Pk current variation reduced by 94 to 97% Energy consumption increased by up to 16% Execution time increased by up to 29% Radu Muresan Waveform Run Time [μs] Energy [μJ] Max S [m. A] Pk. Pk [m. A] blue 21. 3 6. 04 167. 7 2. 47 22. 4 red 21. 3 6. 14 168. 5 1. 87 19. 2 mag. 23. 7 6. 47 144. 0 0. 38 1. 2 black 27. 5 7. 01 134. 0 0. 13 0. 6 Data analysis for hardware flattening CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 17

Conclusions o o The paper presented the mechanisms of the internal current flattening technique (ICF) ICF controls power consumption and current variation n o Countermeasure against PAAs Limitations n Radu Muresan Increased execution time and energy consumption CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 18

Future Work o o Investigate an ASIC implementation of the PAAR architecture Methods to improve the performance and energy consumption of implementations using ICF Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 19

References Used for the Presentation o o o Slides 3 and 4 n W. Mao, “Modern Cryptography”, Prentice Hall, 2004 n O. Kommerling, M. G. Kuhn, “Design principles for tamper-resistant smartcard processors”, In Workshop on Smartcard Technology 1999 Slides 5, 6 and 7 n J-S. Coron, “Resistance against dpa for elliptic curve cryptosystems”, CHES’ 99 n P. Kocher, et al. , “Differential power analysis”, In CRYPTO’ 99 Slide 9 n R. Muresan, C. Gebotys, “Instantaneous current modeling in a complex vliw processor core”, In ACM TECS, 2004 Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 20

THANK YOU! Questions? Radu Muresan CODES+ISSS'04, September 8 -10, 2004, Stockholm, Sweden 21