Chapters 4 5 LC3 Computer Architecture Machine Instructions

Chapters 4 & 5: LC-3 Computer • Architecture • Machine Instructions • Assembly language • Programming in Machine and Assembly Language

Overview The LC-3 Computer 16 bit machine, word addressable, 64 K or 65, 536 locations Computer Machine Instructions – Computer “native” instructions - The basic instructions that all programs use on that computer (The “atomic” unit of work done by a computer) The Instruction Cycle - The steps in the execution of a machine language instruction (Fetch, Decode, Evaluate Address(es), Fetch operand(s), Execute, and Store results)

LC-3 Data Path: Combinational Logic Storage State Machine

Data Path of the LC-3

LC-3 Memory Layout x 0000 – x 2 FFF System: Operating System programs, tables, and data - Generally off limits to programmer (Programs run in Supervisor mode) x 3000 – x. FDFF User: User Program and Data Area shared by users like you (Nominally run in non-supervisor mode) x. FE 00 – x. FFFF Device: I/O Register Addresses Pseudo memory used for input/output R 0 -R 7 Registers (16 bit)

LC-3 Memory Map

Computer Machine Instruction Formats What is IN an instruction? • Operation code – what to do • Input Operand(s) – where to get input operands (memory, registers) • Output Operand(s) – Where to put results (memory, registers) What are the major instruction types? • Data Movement (load, store, etc. ) • Operate (add, sub, mult, OR, AND, etc. ) • Control (branch, jump to subroutine, etc. )

The Instruction Cycle Steps (or phases): • Fetch Next Instruction from Memory (PC) (points to) next instruction PC (PC) + 1 • Decode Fetched Instruction • Evaluate Address (es) (find where the data is) • Fetch Operand (s) (get data) • Execute Operation • Store Result (if specified)

The LC-3 Instruction Addressing Modes • Register (Operand is in one of the 8 registers) • PC-relative (Operand is “offset” from the (PC) ) • Base + Offset (Base relative) (Operand is “offset” from the contents of a register) • Immediate (Operand is in the instruction) • Indirect (The “Operand” actually points to the real address – rather than being the operand)

The LC-3 Instruction Addressing Modes • Register (Operand is in one of the 8 registers) • Immediate (Operand is in the instruction) • PC-relative (Operand is “offset” from the (PC) ) • Indirect (The “Operand” actually points to the real address – rather than being the operand) • Base + Offset (Base relative) (Operand is “offset” from the contents of a register) Note: no Direct Addressing defined in the LC-3

LC-3 Instructions (Fig 5. 3 – Appendix a)

Operate Instructions • Only three operations: ADD, AND, NOT • Source and Destination operands are: Registers

ADD/AND (Register)

NOT (Register) Note: Src and Dst could be the same register.

ADD/AND (Immediate) Note: Immediate field is sign-extended.

Data Movement Instructions • Load -- read data from memory to register – LD: – LDI: – LDR: PC-relative mode indirect mode base+offset mode [0010 DR PCoffset 9] [1010 DR PCoffset 9] [0110 DR Base. R offset 6] • Store -- write data from register to memory – ST: – STI: – STR: PC-relative mode indirect mode base+offset mode [0011 DR PCoffset 9] [1011 DR PCoffset 9] [0111 DR Base. R offset 6] • Load effective address – address saved in register – LEA: immediate mode [1110 DR PCoffset 9]

LD (PC-Relative)

ST (PC-Relative)

LDI (Indirect)

STI (Indirect)

LDR (Base+Offset)

STR (Base+Offset)

LEA (Immediate)

Branch Instruction BR [0000 nzp PCoffset 9] • Branch specifies one or more condition codes • If the set bit is specified, the branch is taken: – PC is set to the address specified in the instruction – Target address is made by adding SEXT(IR[8: 0]) to the PC • If the branch is not taken: - the next sequential instruction (PC) is executed.

BR /////// + SEXT

Jump Instruction JMP Base. R [1100 000 Base. R 000000] • Jump is an unconditional branch -- always taken. • Base – Address is contents of the register – Allows any target address.

TRAP • Calls a service routine, identified by 8 -bit “trap vector. ” vector routine x 23 input a character from the keyboard x 21 output a character to the monitor x 25 halt the program • When routine is done, PC is set to the instruction following TRAP.

TRAPS

Using Branch Instructions • Compute sum of 12 integers. Numbers start at location x 3100. Program starts at location x 3000. R 1 x 3100 R 3 0 R 2 12 R 2=0? NO R 4 R 3 R 1 R 2 M[R 1] R 3+R 4 R 1+1 R 2 -1 YES R 3: Accumulator for the sum of integers R 1: Array index pointer (Begin with location 3100) R 4: Temporary register to store next integer R 2: Loop counter (Count down from 12)

Sample Program Address Instruction Comments x 3000 1 1 1 0 0 0 1 1 1 1 1 R 1 x 3100 (PC+0 x. FF) x 3001 0 1 0 1 1 1 0 0 0 R 3 0 x 3002 0 1 0 1 0 1 0 0 0 R 2 0 x 3003 0 0 0 1 0 1 0 1 1 0 0 R 2 12 x 3004 0 0 0 1 0 0 0 0 1 If Z, goto x 300 A (PC+5) x 3005 0 1 1 0 0 0 0 1 0 0 0 Load next value to R 4 x 3006 0 0 0 1 1 0 0 0 1 Add to R 3 x 3007 0 0 0 1 1 0 0 1 Increment R 1 (pointer) X 3008 0 0 0 1 0 1 1 1 1 Decrement R 2 (counter) x 3009 0 0 1 1 1 1 1 0 Goto x 3004 (PC-6)

Example 1: Multiply • This program multiplies two unsigned integers in R 4 and R 5. clear R 2 add R 4 to R 2 decrement R 5 No R 5 = 0? Yes HALT x 3200 x 3201 x 3202 x 3203 x 3204 01010100000 00010100100 0001101101111111 000001111101 1111000000100101 R 2 <- 0 R 2 <- R 2 + R 4 R 5 <- R 5 – 1 BRzp x 3201 HALT