CDA 3101 Spring 2020 Introduction to Computer Organization

CDA 3101 Spring 2020 Introduction to Computer Organization Instruction Set Architecture MIPS Instruction Format 21 January 2020

The Instruction Set Architecture Application (browser) Software Compiler Assembler Operating System (Linux, Win) Instruction Set Architecture (ISA) Datapath & Control Hardware Memory Digital Logic Circuit Design Transistors I/O System

Overview of the ISA Level • ISA: how the machine appears to a machine language programmer (compiler) – Memory model – Instructions • Formats • Types (arithmetic, logical, data transfer, and flow control) • Modes (kernel and user) – Operands • Registers • Data types • Addressing • ISA formal defining documents – A good example is the Java Virtual Machine (JVM) docs. oracle. com/javase/specs/jvms/se 7/jvms 7. pdf

Computing Languages

Computing Languages High-level Language temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; TEMP = V(K) = V(K+1) = TEMP C/Java Compiler Fortran Compiler lw lw sw sw Assembly Language $t 0, $t 1, $t 0, 0($2) 4($2) MIPS Assembler Machine Language 0000 1010 1100 0101 1001 1111 0110 1000 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111

Program Execution Datapath Memory 0000 1010 1100 0101 1001 1111 0110 1000 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111 . . . program & data I/O Control Fetch – Decode – Execute Cycle

MIPS Machine Language • Arithmetic – add, sub, mult, div • Logical Basic MIPS subset we will use for building MIPS datapath in CDA 3101 – and, or, ssl (shift left logical), srl (shift right logical) • Data transfer – lw (load word), sw (store word) – lui (load unsigned immediate constant) • Branches – Conditional: beq, bne, slt – Unconditional: j (jump), jr (jump register), jal

Design Principles (thus far…) • DP 1: Faster is Better • DP 2: Smaller is Faster (is better …) • DP 3: Keep It Simple and Stupid (KISS) • DP 4: Make the Common Case FAST

MIPS Instructions • Simple (rigid format) instructions (KISS principle) – DP 5: Simplicity favors Regularity add a, b, c # a = b + c; Exactly 3 operands (registers) − Given: add a, b, add a, a, comment a=b+c+d+e; c d Format: <opcode> <input 2> e <output> <input 1> • These instructions are symbolic representations of what MIPS actually understands

Example Compiling a C assignment statement into MIPS f = (g + h) – (i + j); add t 0, g, h add t 1, i, j sub f, t 0, t 1 # temporary variable t 0 contains g+h # temporary variable t 1 contains i+j # f gets the final result In MIPS, t 0 and t 1 are register names

Operands • Operands cannot be any variable (as in C) – KISS principle – avoid CISC pitfalls • Registers – Limited number (32 32 -bit registers in MIPS) • DP 2: Smaller is faster – Naming: numbers or names • $8 - $15 => $t 0 - $t 7 (correspond to temporary variables) • $16 - $22 => $s 0 - $s 8 (correspond to C variables) • Names make your code more readable f = (g + h) – (i + j); $s 0 $s 1 $s 2 $s 3 $s 4 add $t 0, $s 1, $s 2 add $t 1, $s 3, $s 4 sub $s 0, $t 1

Register Conventions Name $zero $at $v 0 -$v 1 $a 0 -$a 3 $t 0 -$t 7 $s 0 -$s 7 $t 8 -$t 9 $k 0 -$k 1 $gp $sp $fp $ra Register Number 0 1 2 -3 4 -7 8 -15 16 -23 24 -25 26 -27 28 29 30 31 Usage the constant value 0 reserved for the assembler value for results and expressions arguments (procedures/functions) temporaries saved more temporaries reserved for the operating system global pointer stack pointer frame pointer return address Preserved on call n. a. no yes no n. a. yes yes

Stored-Program Concept • Instructions are represented as 32 -bit numbers • Programs can be stored in memory – Can be read/written just like numbers Payroll program Payroll data Processor Word processor Term paper Fetch-decode-execute cycle C compiler Source C program

Memory • Contains instructions and data of a program – Instructions are fetched automatically by the control – Data has to be transferred explicitly back and forth between memory and processor • Data transfer instructions load (lw) . . . register file processor save (sw) address data 0 1 2 3 4 Byte (8 bits) . . . word memory

Memory Model • Memory is byte addressable (1 byte = 8 bits) • Only load/store can access memory data • Unit of transfer: word (4 bytes) – M[0], M[4 n], …. , M[4, 294, 967, 292] • Words must be aligned – Words start at addresses 0, 4, … 4 n • Addresses are 32 bits long – 232 bytes or 230 words

Load / Store A[0] = h + A[2]; lw $t 0, 8($s 1) add $t 0, $s 2, $t 0 sw $t 0, 0($s 1) Base address ($s 1) . . . 4 n 4 n+1 A[0] 4 n+2 Offset (8) 4 n+3 4 n+4 4 n+5 A[1] 4 n+6 4 n+7 4 n+8 $s 0 $s 1 4 n $s 2 h registers 4 n+9 4 n+10 4 n+11 . . . A[2]

Big and Little Endian (3101)10 = 12 * 162 + 1 * 161 + 13 * 160 = (00 00 0 c 1 d)16. . . 4 n 00 4 n 4 n+1 00 4 n+1 1 d 0 c 4 n+2 00 4 n+3 1 d 4 n+3 00 . . . big endian . . . little endian

Review • ISA: hardware / software interface • MIPS instructions – Arithmetic: add $t 0, $s 1 – Data transfer: lw/sw, for example: sw $t 1, 8($s 1) • Operands must be registers – 32 32 -bit registers – $t 0 - $t 7 => $8 - $15 (addresses) – $s 0 - $s 7 => $16 - $23 (addresses) • Memory: large, single dimension array of bytes M[232] – Memory address is an index into that array of bytes – Aligned words: M[0], M[4], M[8], …. M[4, 294, 967, 292] – Big/little endian byte order

Conclusions • ISA should outlast technology trends • DP 1: Faster is Better (Performance = Speed) • DP 2: Smaller is Faster – A few registers replace C variables • DP 3: Keep It Simple and Stupid (KISS) – Simple instructions (avoid CISC pitfalls) • MIPS memory model – Byte addressable, Aligned, Linear array • Next Class: START MIPS Programming • Quiz #1 (Digital Logic) Thursday 23 Jan !!