Appendix A Classifying Instruction Set Architecture Memory addressing

Appendix A • Classifying Instruction Set Architecture • Memory addressing mode • Operations in the instruction set • Control flow instructions • Instruction format CDA 5155 Fall 2014, Peir / University of Florida 1

Classifying Architectures • One important classification scheme is by the type of addressing modes supported. – Stack architecture: Operands implicitly on top of a stack. (Early machines, Intel floating-point. ) – Accumulator architecture: One operand is implicitly an accumulator (a special register). (Early machines. ) – General-purpose register architecture: Operands may be any of a large (typically 10 s-100 s) # of registers. • Register-memory architectures: One op may be memory. • Load-store architectures: All ops are registers, except in special load and store instructions. 2

Four Architecture Classes Assembly for C: =A+B: Each instruction has an opcode and one or more operands 3

Number of Operands • A further classification is by the maximum number of operands, and # that can be memory: e. g. , – 2 -operand (e. g. a += b) • src/dest(reg), src(reg) • src/dest(reg), src(mem) IBM 360, x 86, 68 k • src/dest(mem), src(mem) VAX – 3 -operand (e. g. a = b+c) • dest(reg), src 1(reg), src 2(reg) MIPS, PPC, SPARC, &c. • dest(reg), src 1(reg), src 2(mem) IBM 370 • dest(mem), src 1(mem), src 2(mem) IBM 370, VAX 4

Endians & Alignment 7 6 5 4 3 2 1 Increasing byte address 0 Byte addressable memory 4 Word-aligned word at byte address 4. 2 Halfword-aligned word at byte address 2. 1 Byte-aligned (non-aligned) word, at byte address 1. word 3 (MSB) 2 1 0 (LSB) word 0 (LSB) 1 2 3 (MSB) Little-endian byte order (least-significant byte “first”). Big-endian byte order (most-significant byte “first”). 5

Addressing Modes Scaled add r 1, 100(r 2)[r 3] R[1] + M[100+R[2]+R[3]*d • In example assembly syntax in middle column, ( ) indicates memory access. (A typical syntax. ) • In RTL syntax on right, [ ] denotes accessing a member of an array, Register or Memory. 6

Addressing Mode Usage 3 SPEC 89 on VAX 7

Displacement Distribution SPEC CPU 2000 on Alpha Sign bit is not counted 8

Use of Immediate Operand SPEC CPU 2000 on Alpha 9

Distribution of Immediate SPEC CPU 2000 on Alpha Sign bit is not counted 10

Instruction Type (Same as A. 12 in the 5 th Edition) 11

Instruction Distribution (Same as Fig. A. 13) (5 SPECint 92) 12

Control Flow Instructions • Four basic types: – – (Conditional) branches (Unconditional) jumps Procedure calls Procedure returns • Control flow addressing modes: – Often PC-relative (PC + displacement). Relocatable. – Also useful: register indirect jumps (reg. has addr. ). Uses for: • Procedure returns • Case / switch statements • Virtual functions / methods (abstract class method calls) • High-order functions / function pointers • Dynamically shared libraries 13

Conditional Branch Options q Need evaluate condition and branch to target • Condition Code (CC) Register – E. g. : X 86, ARM, PPC, SPARC, … – ALU ops set condition code flags in the CCR – Branch just checks the flag • Condition register – E. g. : Alpha, MIPS – Comparison instruction puts result in a GPR – Branch instruction checks the register • Compare & Branch – E. g. : PA-RISC, VAX, BEQZ, BNE in MIPS – Compare & branch in 1 instruction. 14

Procedure Calling Conventions • Two major calling conventions (for saving & restoring registers): – Caller saves: • Before the call, procedure caller saves registers that will be needed later, even if callee did not use them – Callee saves: • Inside the call, called procedure saves registers that it will overwrite • Can be more efficient if many small procedures • Many architectures use a combination of schemes: – E. g. , MIPS: Some registers caller-saves, some callee-saves 15

Three Classes of Control Instructions SPEC CPU 2000 on Alpha 16

Branch Distance Distribution SPEC CPU 2000 on Alpha 17

Branch Comparison Types SPEC CPU 2000 on Alpha 18

Encoding An Instruction Set 19

Example: MIPS 32 r 0 r 1 ° ° ° r 31 PC lo hi 0 Programmable storage Data types ? 2^32 x bytes Format ? 31 x 32 -bit GPRs (R 0=0) Addressing Modes? 32 x 32 -bit FP regs (paired DP) HI, LO, PC Arithmetic logical Add, Add. U, Sub. U, And, Or, Xor, Nor, SLTU, Add. IU, SLTIU, And. I, Or. I, Xor. I, LUI SLL, SRA, SLLV, SRAV Memory Access LB, LBU, LHU, LWL, LWR SB, SH, SWL, SWR Control 32 -bit instructions on word boundary J, JAL, JR, JALR BEq, BNE, BLEZ, BGTZ, BLTZ, BGEZ, BLTZAL, BGEZAL

MIPS 64 Architecture • RISC, load-store architecture, simple address • 32 -bit instructions, fixed format • 32 64 -bit GPRs, R 0 -R 31. – Really, only 31 – R 0 is just a constant 0. • 32 64 -bit FPRs, F 0 -F 31 – Can hold 32 -bit floats also (with other ½ unused). – “SIMD” extensions operate on more floats in single FPR • A few special registers – Floating-point status register • Load/store 8 -, 16 -, 32 -, 64 -bit integers – All sign-extended to fill 64 -bit GPR – Also 32 - bit floats/doubles 21

MIPS 64 Addressing Modes • Register (arith. /logical ops only) – 64 bit integer, 32 or 64 floating-point; Inst. is fixed 32 bits • Immediate (arith. /logical only) & Displacement (load/stores only) – 16 -bit immediate / offset field – Register indirect: use 0 as displacement offset – Direct (absolute): use R 0 as displacement base • Byte-addressed memory, 64 -bit address • Software-settable big-endian/little-endian flag • Alignment required • Note, the course project works on MIPS 32 22

Inst. Format: I-type Instructions Immediate (16 bits) for imme. operand for Displacement 23

Inst. Format: R-type Instructions à à NOTE, R-R ALU only need 21 bits: opcode+rs+rt+rd Shamt is for shift amount for bit-level operation Funct is for function code; only one Opcode for RR ALU More details see MIPS code map!! 24

Inst. Format: J-type Instructions 25

MIPS Instruction Set • MIPS ISA in Figures A. 23 -26 • The MIPS 32™ ISA manual provides more details for 32 -bit arch. : http: //www. cise. ufl. edu/class/cda 5155 fa 12/projects/project 1/mips. pdf • Branch and Jump Addresses – PC-relative addressing: • Branch target address = (PC+4) + (Displacement || “ 00”); Note instead of PC, (PC+4) for hardware convenience and the two zeros is added due to word displacement / alignment. – Jump (limited to 256 MB range): • (Upper 4 bits of Current PC) || (26 -bits address in Jump) || (“ 00”) – Long Jump: • Jump register: save 32 -bit target address in register 26

MIPS registers and usage convention 27

MIPS Code Map 28

MIPS Code Map FIGURE A. 10. 2 MIPS opcode map. The values of each field are shown to its left. The first column shows the values in base 10, and the second shows base 16 for the op field (bits 31 to 26) in the third column. This op field completely specifies the MIPS operation except for six op alues:  0, 1, 16, 17, 18, and 19. These operations are determined by other fields, identified by pointers. The last field (funct) uses “f ” to mean “s” if rs = 16 and op = 17 or “d” if rs = 17 and op = 17. The second field (rs) uses “z” to mean “ 0”, “ 1”, “ 2”, or “ 3” if op = 16, 17, 18, or 19, respectively. If rs = 16, the operation is specified elsewhere: if z = 0, the operations are specified in the fourth field (bits 4 to 0); if z = 1, then the operations are in the last field with f = s. If rs = 17 and z = 1, then the operations are in the last field with f = d. 29