Unit II The ARM processor Beagle Bone Beagle

Unit - II The ARM processor

Beagle Bone : • • Beagle Boardx. M Beagle Bone White Beagle Bone Black • Based on ARM cortex A 8 • 512 DDR 3 RAM • 4 GB on board Storage

Introduction to Beagle Boards : • Beagle boards are tiny computers with all the capabilities of today’s desktop machine. • To teach open source hardware and software capabilities • Produced by Texas Instruments in association with Digi. Key and Newark element 14 • Developed as a demonstration of OMAP (Open Multimedia Application platform) System on Chip (Soc) • CPU: ARM Cortex A 8 • Supported OS: Linux, Minix, Free. BSD, Android, Symbian, RISC OS

Beagleboard – Rev. C

Hardware - Beagleboard OMAP 3530 (Soc) forms the core of the board. Uses Package on Package stacking of memory on top of OMAP Memory: Interfaces: 256 MB NAND, 256 MB DDR SDRAM DVI-D (via HDMI connector), JTAG, RS 232, USB 2 OTG Stereo In, Stereo Out, S-Video, USB 2 Host Expansion Header: I 2 C, I 2 S, SPI, MMC/SD Can be USB bus powered or take DC power

Using the Beagleboard Booting: NAND -> USB-> UART -> MMC (For Beagle Board) USB -> UART -> MMC -> NAND (For processor) Uses U-Boot (Universal Boot loader) Provides a simple Command Line Interface to manipulate hardware prior to booting a kernel MMC/SD is the only way to bring up a new board.

Beagleboard - Software Distributions you can use: Angstrom Ubuntu Android (Google’s open source software stack for mobile devices) Number of other embedded Linux distros.

Developing for Beagleboard Openembedded (OE): Provides an easy to use build environment Collection of metadata about software packages support for many hardware architectures runs on any Linux distribution Cross Compilation Other options: Use the Android SDK Build your own toolchain Start from a ready made image

Beagle. Bone • Announced in the end of October 2011 • The Beagle. Bone is a barebone development board with a Sitara ARM Cortex-A 8 processor • 720 MHz, 256 MB of RAM • Two 46 -pin expansion connectors • On-chip Ethernet • A micro. SD slot and a USB host port • A device port which includes low-level serial control and JTAG hardware debug connections, so no JTAG emulator is required.

Beagle. Bone Features : • • Built-in networking Remote access File system Use many different programming languages Multitasking Linux software Open Source

Beagle. Bone Black

Component Locations

Connector and switch Locations

4 LEDs

Lets start with basic: LEDS • There are four user LED(s) on the Beaglebone. The user LED(s) are • Accessible from user space on the file system at this location: /sys/class/leds/ • There is one directory per user LED, named as shown below: • • /sys/class/leds/beaglebone: : usr 0/ (GPIO 1_21) /sys/class/leds/beaglebone: : usr 1/ (GPIO 2_22) /sys/class/leds/beaglebone: : usr 2/ (GPIO 2_23) /sys/class/leds/beaglebone: : usr 3/ (GPIO 2_24)

On-board LED: • Write the following commands in your terminal (First one is for turning ON and latter for OFF): • USER 0 : heartbeat indicator from the Linux kernel. • USER 1 : SD card access • USER 2 : activity indicator. Turns on when the kernel is not in the idle loop. • USER 3 : Onboard e. MMC is access.

Comparison :

U-Boot : • • • Universal Boot loader for embedded systems Locating and loading the kernel with the set arguments Setting up the arguments Initializing additional hardware Makes booting from serial and USB port possible

Boot Modes : • e. MMC Boot (MMC 1) • Uses onboard memory • Default boot mode • Fastest • SD Boot (MMC 0) • u. SD card • Serial Boot • Boots from serial ports • USB Boot (USB 0) • Boots from USB

Booting Options : • Without holding the boot button : • • e. MMC Boot u. SD Boot Serial Boot USB Boot • Holding the boot button : • u. SD Boot • USB Boot • Serial Boot

BBB interfacing : • Initialization • Export • Input • Direction • Logic • Changing the values • Output • Direction

BBB interfacing with Stepper Motor Connector Number BBB PIN Number P 9 1, 2 P 9 PIN Description PIN connects to stepper motor connected FRC Function GND(25 pin) GND 5 VCC(5 V) VCC(26 pin) VCC P 9 11 GPIO 0[30] FRC-21 pin Out P 9 12 GPIO 1[28] FRC-22 pin Out P 9 13 GPIO 0[31] FRC-19 pin Out P 9 14 GPIO 1[18] FRC-20 pin Out

Embedded System Processors • A number of choice available for embedded processors • Two categories are: • Standalone Processors • Requires external chipset to form complete system • Integrated Processors • So. C: System on Chip

Standalone Processors • Dedicated exclusively to the processor functions • Needs external controllers to interfacing with surroundings. E. g. DRAM controller, keyboard controller and serial ports • Highest Overall CPU performance.

Standalone Microprocessor Based System

Standalone Processors: Example • Many standalone processors in 32 bit and 64 bit exist and widely used in embedded systems: • IBM 970 FX : • A high performing 64 bit capable stand alone processor. • Superscalar architecture: Core can fetch, decode and execute for more than one instruction at a time (Deeply Pipelined) • Used also in IBM blade server platform

Standalone Processors: Example • Intel Pentium M • One of the most popular x 86 architecture for 32 and 64 bit. • Super scalar architecture like IBM 970 FX. • Used in many earlier laptops and commercial embedded systems Intel Atom • Widely used in notebooks and embedded system applications. Known for low power consumption

Integrated Processor : So. C

So. C • A microchip that has all the components to run the system. • Integrates all the components of computer in a single chip • Majority of embedded application uses Integrated processors (So. C) • Beagleboard • Processor TI OMAP 3530 So. C - 720 MHz ARM Cortex-A 8 core

ARM TIMELINE : • 1985: Acorn Computer Group manufactures the first commercial RISC microprocessor. (ARM – I. . . V) • 1990: Acorn, Apple and VLSI based Technology group = Advanced RISC Machines (A. R. M. ). • 1991: ARM 6, First embeddable RISC microprocessor. • 1993 : ARM 7, the first multimedia microprocessor is introduced. • Users : • • Samsung Atmel Philips Etc.

ARM :

Advanced RISC Machine : • Instructions are same size : 32 bit • Instructions are executed in 1 cycle • Load/Store access memory • Advantage: • Number of transistors are less compared to similar CISC architecture. • Less hardware results in less die size • Low power consumption

Advanced Features • Thumb: • A new 16 bit instruction set called thumb is made available. • This is less powerful instruction set but quite useful for application that do not require full power of 32 bit instructions. • Advantage: High Code Density • (Higher amount of code in per unit memory area) • MMU and MPU: • Desktop system requires it. • It depends on application requirement in embedded system • ARM processor can be implemented with MMU and MPU or with one of them or neither of them.

Advanced Features • Debug Interface: • There is chip testing unit called JTAG (joint testing action group) interface. • JTAG standard defines a set of interface for testing hardware and initial code. • Jazalle DBX: (Direct Byte code Execution) • Some ARM processors have direct execution support for byte code in hardware. • Useful in devices for execution games and java application that otherwise require a heavy JVM.

Advanced Features • Vector Floating Point Unit • Hardware support for floating point computation • Cache: • The first ARM processor with Cache is ARM 3. It had 1 KB chip of 4 KB. • ARM 7 had a cache of 8 KB.

Advanced Features • Fast Multiplier • Even though ARM is a RISC processor, there are many features that do not conform to RISC philosophy • ARM processors may have a fast multiplier hardware unit. • Synthesizable: • Design Code (RTL) is available with License, using which extensions and modification are possible in basic core

Advanced Features • Embedded ICE (In Circuit Emulator) Macrocell: • The current hardware trend is to design system as macrocells. • The ARM core could be considered as macrocell and other units may also be added as (e. g. peripheral units) macrocells. • Some processor has embedded ICE macrocell for testing. • Used for debugging and have registers to set watch points and breakpoints.

Naming Conventions for ARM • Example: ARM 7 TDMI

ARM CORTEX • Latest in ARM is cortex series • Based on architecture V 7 version: • THUMB-2 technology (Both 16 and 32 bit supported) • No need to switch between ARM and THUMB instruction set • Cortex has well defined profile for different application areas: • A • R • M

Cortex Profiles • A profile: • For High End applications in Embedded Systems with modern OS. (e. g. Android) • ARMv 7 -A architecture • Used in Mobile phones and Video Systems • R Profile: • For high end application on systems with Real time capabilities • ARMv 7 -R architecture • Used in safety critical systems • M profile: • Designed for Core embedded microcontroller type systems • ARMv 7 -M architecture • Used in control applications

Advanced Features : • Data bus width : • 32 bit data bus • 32 bit read/write in 1 cycle • Computational capability: • RISC Approach provides good computations • RISC architecture with few CISC add-ons • Low Power: • Power saving • Operates at low clock frequencies • 60 MHz to 1 GHz

Advanced Features : • Multiple Register Instructions : • Data processing with registers mostly • Processing instructions do not use addressing modes that uses one operand in memory. • But, instructions for loading and storing data to registers. • DSP Enhancement: • Additional DSP features

Pipelining : • Dividing instruction processing in sub-stages • 3 Stage pipeline: (ARM-7) • Fetch – Decode – Execute • 5 Stage Pipeline: (ARM-9) • Fetch – Decode – Execute – Buffer - Write • (ARM-10) – 6 stage pipeline • Drawback: • • Problem with branch instructions Due to sequence change some instructions are discarded Loss of data, computation time Higher penalty with more stages

Instruction Set Architecture • Programmers view of computer architecture • Consists of : • Instruction Sets • Addressing Modes • Registers etc. • Basic ISA of all ARM processor are more or less same

CPSR (Current Program Status Register) Bit Nos. Notion Interpretation 0 to 4 Mode Specifies the current mode of operation 5 T State : ARM = 1 or THUMB = 0 6 F Disables (F=1) FIQ 7 I Disables (I=1) IRQ 8 to 23 Undefined 25 to 26 Undefined 24 J J=1 means in Jazalle state 27 Q Sticky Overflow flag 28 to 31 VCZN Condition flags

CPSR N: Negative (N=1 indicates negative results) Z: Zero ( Z=1 indicates result is 0) C: Carry V: Overflow

Exception Priorities : • • • Reset (Highest) Data abort FIQ IRQ Prefetch abort SWI, undefined instruction (Lowest)

Data Type • 6 data types in all: • Signed and unsigned • 32 bit/ 16 bit and 8 bit operations supported • Processing tool offers the option of storing data in little endian and big endian formats • Data Alignment: • For word (32 -bit) should have least 2 bits of address as 0 • Eg: 0 x 1200 • For unaligned data like 0 X 1201 • (32 – bit ) will access 2 memory cycles 1 @ 0 x 12001, 2 @ 0 x 1204

Assembly Language Rules : • • Label Opcode / Instruction field Operand field Comment • Label ADD R 1, R 2, R 3 ; Add instruction

Shift and Rotate • Two types of shifts are possible • Logical and Arithmetic • LSL (Logical Shift Left): • For a 32 bit register, shift left (a specified number of times) results in shifting every bit left and vacant bits at right are filled with zeroes • The last bit shifted out from the left is copied to the carry flag • Left shift by one bit position corresponds to multiplication by 2. • An LSL of 5 implies multiplication by 32

Shift and Rotate • LSR (Logical Shift Right) • Similar to LSL but shifts bits in right • Vacant bits at left filled by zeroes. • The last bit shifted out is retained in carry flag • Shifting right by 1 bit is equivalent to dividing the number by 2. • Two right shift cause a division by 4

Shift and Rotate • ASR (Arithmetic Shift Right): • Vacant bit in the left is filled with MSB of the original number. • This type of shift has the function of doing ‘sign extension’ of data • There is not instruction for Arithmetic Shift Left

Shift and Rotate • ROR (Rotate Right) Data is shifted right The bit shifted out from right is inserted back through left. The last bit rotated out is available in carry flag. There is no Rotate Left instruction, because left rotate ‘n’ times can be achieved by rotating right ‘ 32 -n’ times. • For example rotating 4 times to the left is achieved by rotating 32 -4 = 28 times to the right • •

Shift and Rotate • RRX (Rotate Right Extended): • This corresponds to rotating right though the carry bit. • Bits dropped off from the right side is moved to CF and the carry bit enters through the left of the data.

Format of Shift and Rotate Instruction • The number of bit position by which shift or rotate operation need to be done is specified by a constant or another register. • Example: LSL R 2, #4 ; shift left logically the content of R 2 by 4 bit position ASR R 5, #8 ; Shift right arithmetically the content of R 5 by 8 bit position ROR R 1, R 2 ; Rotate the content of R 1 by the number specified by R 2

Problem • The content of some of the registers are given as: R 1=0 x. EF 00 DE 12 R 2=0 x 0456123 F R 5=4 R 6=28 Find the result in destination register following: • LSL R 1, #8 • ASR R 1, R 5 • ROR R 2, R 6 • LSR R 2, #5

Solution R 1=0 x. EF 00 DE 12 R 2=0 x 0456123 F R 5=4 R 6=28 Find the result in destination register following: LSL R 1, #8 (Ans: 0 x 00 DE 1200) ASR R 1, R 5 (Ans: 0 x. FEF 00 DE 1) ROR R 2, R 6 (Ans: 0 x 456123 F 0) LSR R 2, #5 (Ans: 0 x 0022 B 091)

Combining the operation of Move and Shift MOV R 1, R 2, LSL #2 MOV R 1, R 2, LSR R 3 In both , instruction R 1 is the destination register. In first instruction, the source operand i. e. content of R 2 is logically shifted left twice and then moved to R 1. • In second instruction, amount of shifting is specified by R 3. • •

Problem R 5= 0 x 72340200 and R 2=4 Find MOV R 3, R 5, LSL #3 MOV R 6, R 5, ASR R 2

Problem R 5= 0 x 72340200 and R 2=4 Find MOV R 3, R 5, LSL #3 MOV R 6, R 5, ASR R 2 (R 3=0 x 91 A 01000) (R 6=0 x 07234020)

Conditional Execution • An important and distinguished feature of ARM • Instruction is executed only if specified condition is true. • In general, all data processing instruction are expected to affect conditional flags. • But in ARM, we must suffix the instruction with ‘S’ for this to happen. • ‘S’ suffix in data processing instruction causes the flags in CPSR to be updated.

Example • MOV R 3, R 5, LSL #3 • No affect on carry flat and N flag in CPSR • MOVS R 3, R 5, LSL #3 • The MOV instruction is made conditional by suffixing it with S. • C and N flags are now set. • This flag setting can be used to make an instruction following it to be conditional.

Recap: Carry Flag • The carry (C) flag is set when an operation results in a carry, or when a subtraction results in no borrow. • In ARM, C is set in one of the following ways: • For an addition, C is set to 1 if the addition produced a carry (that is, an unsigned overflow), and to 0 otherwise. • For a subtraction, including the comparison instruction CMP, C is set to 0 if the subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise. • For non-additions/subtractions that incorporate a shift operation, C is set to the last bit shifted out of the value by the shifter. • For other non-additions/subtractions, C is normally left unchanged.

Detailed Format :

Detailed Format :

Question : • What will be the result : • • • ADD R 1, R 2, LSL #3 RSB R 3, LSL #3 RSB R 3, R 2, LSL #4 SUB R 0, LSL #2 RSB R 2, R 1, #0

Solution : • What will be the result : • • • ADD R 1, R 2, LSL #3 RSB R 3, LSL #3 RSB R 3, R 2, LSL #4 SUB R 0, LSL #2 RSB R 2, R 1, #0 R 1 = R 2 + 8 R 2 R 3 = 8 R 3 – R 3 = 16 R 2 – R 2 R 0 = R 0 – 4 R 0 R 2 = 0 – R 1

Q. Write a small assembly program for ARM, required that 2 numbers stored in R 1 and R 2 registers, the bigger num is to be placed in R 10, if 2 num are equal Put it in R 9.

Q. Write a small assembly program for ARM, required that 2 numbers stored in R 1 and R 2 registers, the bigger num is to be placed in R 10, if 2 num are equal Put it in R 9. SUBS R 3, R 1, R 2 MOVEQ R 9, R 1 MOVHI R 10, R 1 ; R 3 = R 1 – R 2 ; IF R 1=R 2 / Z=1. . . R 1 -> R 9 ; IF R 1 > R 2 / C=1. . . R 1 -> R 10 ; MOV R 10, R 2 ; MOVLS R 10, R 2 ; if R 1<=R 2 , C=0|Z=1 , move R 2 to R 10

Flag setting after compare Instruction If C Z R 3>R 4 1 0 R 3<R 4 0 0 R 3=R 4 1 1

TST Instruction • TST is similar to compare, but it does ANDing and then sets conditional flags. • If the result of ANDing is zero, then zero flag is set. • It can be used to verify at least one of the bits of a data word is set or not. • Write instruction to verify the LSB of a word in register R 1 is set or not. • TST R 1, #01

TEQ Instruction • TEQ does exclusive ORing which tests for equality. • If both operands are equal then only zero flag is set. • TEQ R 1, #45

Data Processing Instructions :

Multiplication :

Example : • MUL R 1, R 2, R 3 • MULSEQ R 1, R 2, R 3 • MULEQ R 1, R 2, R 3 • UMULL R 1, R 2, R 3, R 4

Branch Instructions : • • B BL BX BLX Branch and Link Branch and Exchange with Link • Eg : • • <Label> STOP <Label> B B BNE BHI New STOP New

Assembly Programming in ARM • Two kind of statements : • Executable statements • Directives (related to assembler) • • • AREA ENTRY RN END Defining data

Directives : • ENTRY • Entry point of first executable instruction • END • AREA <NAME_OF_REGEION> , CODE/DATA, READONLY/READWRITE • Eg. AREA SORT, CODE, READONLY

Directives : • Defining Data • NUMS • NUM 1 • NUM 2 DCB DCW DCD 9, 10, 15 0 x 6787, 0 x 4565 0 x 00000123, 0 x 67890900 • RN • Giving variable names to registers • X RN 1 • Y RN 10 • EQU • Equate • FACT • ASD EQU 35 0 x 4000

Question : • Write a program to find 3 X + 4 Y + 9 Z , • WHERE X = 2 • Y=3 • Z= 4

Program to calculate factorial of 5 numbers • Write down an ARM assembly program to calculate factorial of 5. • • Instructions Involved: MUL SUBS BNE

Solution AREA FACTO, CODE ENTRY MOV R 1, #5 MOV R 2, #1 REPT MUL R 2, R 1 SUBS R 1, #1 BNE REPT B B STOP END ; Define the code area ; entry point ; R 1=5 ; R 2=1 ; R 2=R 2 XR 1 ; R 1=R 1 -1 ; Branch to REPT if Z!=0 ; last line ; End

Subroutine/Procedures • Another kind of branch used in Subroutine calls – BL (Branch and Link) • When a BL encountered (control transfer to new sequence of instruction OR the new procedure) ARM saves current PC value in Link register. • PC then starts with new instruction set (Branch Target). • At the end of procedure , LR is copied to PC

Finding 3 X 2 + 5 Y 2 , where X=8 and Y=5 STOP SQAURE AREA PROCED, CODE ENTRY MOV R 2, #8 BL SQUARE ADD R 1, R 3 , LSL #1 MOV R 2, #5 BL SQUARE ADD R 0, R 3, LSL #2 ADD R 4, R 1, R 0 B STOP MUL R 3, R 2 MOV PC, LR END

Example • The constant value being added to Rn is immed_8 rotated right by 2*rotate_imm.

Constants : • Only decimal values within range 0 – 16320 can be created using this schema. • Instructions MOV, MVN can also be used with ROR

Literal Pools • Literal Pool is a lookup table used to hold literals during assembly and execution. • Literals : Written exactly as it is meant to be interpreted. Example: x=125 ; x is variable, 125 is literal • Take an example of immediate operand • • • MOV R 1, #0 x 3333 Assembler will give error that such constants cannot be generated. To avoid the situation we can write: LDR R 1, = 0 x 3333 (This is a pseudo instruction for assembler)

Literal Pools LDR R 1, =0 x 3333 • The pseudo instruction forces the assembler to check for one of the following possibilities 1. 2. Can the constant be constructed with MOV or MVN combined with rotation? Assembler places the value in literal pool and generated and LDR with program relative address • Memory Space after END • LTORG statement

Example • LDR R 3, [R 2, LSL #2] • The effective address is the content of R 2 left shifted by 2 (multiplied by 4) • STR R 9, [R 1, R 2, ROR #2] • The effective address is specified by R 1 and R 2 and a right rotation • LDR R 4, [R 3, R 2] • The effective address here is sum of R 3 and R 2 • STR R 5, [R 4, R 3, ASL #4] • The effective address is the sum of content of R 4 and the arithmetically left shifted (by 4) content of R 3

Bytes, Half Words and Words • ARM has instruction to transfer specifically a word (32 bits), half word (16 bits) or a byte 8 bits) between memory and registers. Load Instruction Description Store Instruction Description LDR Load Word STR Store Word LDRH Load Half Word STRH Store Half Word LDRSH Load Signed Half Word LDRB Load Byte STRB Store Byte LDR Load Signed Byte

Problem • Memory areas are referenced by two registers • R 1=0 x 00001200, R 2=0 x 40001100 1. 2. 3. 4. Address Byte Stored 0 X 00001200 56 0 X 00001201 23 0 X 00001202 0 D 0 X 00001203 AE LDR R 3, [R 1] LDRB R 3, [R 1] LDRH R 3, [R 1] STRB R 3, [R 2], provided that R 3= 0 x 00002356

Solution: LDR R 3, [R 1] • R 3 = 0 x. AE 0 D 2356 • LDRB R 3, [R 1] • R 3 = 0 x 00000056 • LDRH R 3, [R 1] • R 3 = 0 x 00002356 • • STR R 3, [R 2], provided that R 3= 0 x AE 0 D 2356 STRB Address Byte Stored 0 X 40001100 56 0 X 40001101 23 0 X 40001102 0 D 0 X 40001103 AE STRH

Loading Signed Numbers : • R 7 = 0 x. CDEF 8204 • LDRSH • LDRSB R 1, [R 7] R 1 = 0 x. CDEF 8204 R 1 = 0 x. FFFF 8204 R 1 = 0 x 00000004

Indexed Addressing Modes • Pre Indexed Addressing Modes • LDR R 0, [R 7, #4] • R 7 is the base register and effective address is R 7+4. The data at effective address is copied to R 0. • Add ! For write back option • LDR R 0, [R 7, #4]! R 7 = R 7 + 4; • Post Indexed Addressing Mode • LDR R 0, [R 4], #4 • The data pointed by R 4 is first copied to R 0. Then the content of R 4 is changed to R 4+4

Multiple Load and Store (LDM and STM) • Multiple register load means that multiple memory locations are to be accessed and loaded into multiple registers. • There is a base register acting as pointer to the first memory location to be accessed. • The register then incremented or decremented to point the next memory location • LDM/STM{condition} address-mode Rn {!} , reg-list

LDM and STM • Suffixes used with LDM and STM • IA : Increment After • IB : Increment Before • DA : Decrement After • DF : Decrement Before LDMDA R 0, {R 4 -R 9} 32 bit word pointed by R 0 is copied to R 4 32 bit word pointed by R 0 -4 is copied to R 5 32 bit word pointed by R 0 -8 is copied to R 6 and so on. . . . till R 9.

• LDMIA R 10, {R 9, R 1 -R 3} 32 bit word pointed by R 10 is copied to R 1 32 bit word pointed by R 10+4 is copied to R 2 32 bit word pointed by R 10+8 is copied to R 3 32 bit word pointed by R 10+12 is copied to R 9

The STM instruction • Same format as LDM • STMIA R 1, {R 2 -R 4} • • Equivalent to the following instruction SRT R 2, [R 1] STR R 3, [R 1, #4] STR R 4, [R 1, #8]

ARM 9: Major Improvements over ARM 7 • Decreased heat production and lower overheating risk. • Shifting from a three-stage pipeline to a five-stage one lets the clock speed be approximately doubled, on the same silicon fabrication process. • Cycle count improvements. Many unmodified ARM 7 binaries were measured as taking about 30% fewer cycles to execute on ARM 9 cores. • Some ARM 9 cores incorporate "Enhanced DSP" instructions, such as a multiply-accumulate, to support more efficient implementations of digital signal processing algorithms.

ARM 9 • Implement Harvard Architecture: The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data.

ARM 9: LPC 29 XX ARM MCU • The LPC 29 xx consists of: • An ARM 968 E-S processor with real-time emulation support • An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers • Two DTL buses for interfacing to the interrupt controller • Three or four ARM Peripheral Buses (APB) for connection to on-chip peripherals

ARM 9 : Advanced Microprocessor Bus Architecture • The ARM’s AMBA protocols are an open standard, on-chip interconnect specification. • It specifies the connection and management of functional blocks in a System-on-Chip (So. C). • It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals.

ARM 9 : AHB and APB • AHB stands for Advanced High-performance Bus • APB sands for Advanced (sometimes ARM) Peripheral Bus. • Both are part of the Advanced Microprocessor Bus Architecture (AMBA). • Dedicated AHB to APB bridges are used to interconnect.

ARM Cortex M 3 • Cortex-M 3 Processor • The ARM Cortex-M 3 processor is the industry-leading 32 -bit processor for highly deterministic real-time applications • Specifically developed to enable partners to develop highperformance low-cost platforms for: • • Microcontrollers automotive body systems Industrial control systems wireless networking and sensors • LPC 17 XX