AMICSA 2010 Validation Results of a Radiation Hardened

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AMICSA 2010 Validation Results of a Radiation Hardened 24 -bit Digital-to. Analogue Converter K.

AMICSA 2010 Validation Results of a Radiation Hardened 24 -bit Digital-to. Analogue Converter K. Makris 1, D. Fragopoulos 1, G. Tsiligiannis 1, T. Lambaounas 1, P. Anagnostopoulos 1, C. Papadas 1, J. P. Schoellkopf 2, B. Glass 3 (1) (2) (3) Integrated Systems Development (ISD S. A. ), Athens, GREECE Advanced System Technology and User Service (ASTUS S. A. ), Grenoble, FRANCE European Space Research and Technology Center (ESA/ESTEC) – Microelectronics Section (TEC-EDM), Noordwijk, THE NETHERLANDS

Overview Features Architecture Layout – chip fabrication Package Validation plan overview Validation board and

Overview Features Architecture Layout – chip fabrication Package Validation plan overview Validation board and test setup Electrical test results Digital part Analog part Static performance summary Dynamic performance summary Radiation tests and setup Radiation test results Conclusions and future work AMICSA 2010, September 7 th 2

Product highlights Features Architecture: multi-bit ΣΔ modulator Output stage: differential current steering Digital input

Product highlights Features Architecture: multi-bit ΣΔ modulator Output stage: differential current steering Digital input interface: Synchronous serial data format Bandwidth: 0. 1 m. Hz – 1 k. Hz Sampling frequency: selectable 6 k. Hz or 12 k. Hz Oversampling ratio: selectable x 256 or x 128 Configuration via I 2 C interface 1. 2 V digital power supply 3. 3 V analog power supply Radiation tolerant design Operating modes Normal Bypass Test Power down 1 Digital ON / Current sources OFF / Reference block ON Power down 2 Digital ON / Current sources OFF / Reference block OFF Applications High accuracy instrumentation and actuator drive for systems operating in space AMICSA 2010, September 7 th 3

System Overview DAC 24 BISDA 1. 2 V SDA SCL MCLK Test signals Input

System Overview DAC 24 BISDA 1. 2 V SDA SCL MCLK Test signals Input interface I 2 C interface Clock Distribution network Interpolation stage 3 rd order ΣΔ modulator DWA OUTP 1 DAC 1 (Main) Level Shifters (1. 2 - 3. 3 V) SDIN SCLK SYNC 3. 3 V Reference block OUTM 1 Ref. Voltage OUTP 2 DAC 2 (Redunda nt) OUTM 2 DFT AMICSA 2010, September 7 th 4

Architecture: Digital Part (1/2) 1. 2 V Clock Distribution network SDIN SCLK SYNC IRP

Architecture: Digital Part (1/2) 1. 2 V Clock Distribution network SDIN SCLK SYNC IRP 1 Linear Phase X 2 Digital input interface IRP 2 Halfband X 2 IRP 3 Halfband X 2 Interpolator I 2 C Registers bank Write SDA SCL 3 rd order ΣΔ Modulator Read I 2 C interface Test signals AMICSA 2010, September 7 th DFT block DWA DATAp 1 [31: 0] SINC X 32/X 16 Digital to Analog interface block (Level Shifters) MCLK DATAm 1 [31: 0] CLK 1 PDN_ANA DATAp 2 [31: 0] DATAm 2 [31: 0] CLK 2 DATA [31: 0] 5

Architecture: Digital part (2/2) Modulator design 3 rd order feed-forward ΣΔ modulator 5

Architecture: Digital part (2/2) Modulator design 3 rd order feed-forward ΣΔ modulator 5 -bit quantizer Sampling frequency 6 k. Hz when OSR X 256 and 12 k. Hz when OSR X 128 Idle Tone avoidance by introduction of dither Dynamic Element Matching (DEM) The output element mismatch error is minimized by the use of a DEM algorithm. Data Weighted Averaging (DWA) as an efficient DEM algorithm. Algorithm's objective → achieve an equal use of elements in long-term by rotating the output elements (current sources) in a cyclic fashion. DWA uses only one index, which is updated with the addition of the input every clock cycle. AMICSA 2010, September 7 th 6

Architecture: Analog Part Bandgap cell provides an accurate reference voltage (1. 2 V) with

Architecture: Analog Part Bandgap cell provides an accurate reference voltage (1. 2 V) with a low temperature coefficient. First order RC filter reduces any noise from the bandgap block. Low noise Op-Amp along with M 1 and current setting resistor (Rref or Rext) implements the reference current source for generating the reference current Iref. IRef can be set by selecting the internal resistor RRef or connecting an external resistor Rext. Differential elementary current sources built around the regulated cascode topology. Use of PMOS transistors for lower flicker noise(1/f) and high linearity. AMICSA 2010, September 7 th 7

Radiation hardening techniques Technology level: ST Microelectronics HCMOS 9 0. 13 um is a

Radiation hardening techniques Technology level: ST Microelectronics HCMOS 9 0. 13 um is a rad-hard proven Library level: For the digital part the most oversized and robust standard cells were Digital design level technology. used (including latches and flip-flops). Analogue design level Fault masking by TMR (e. g. FSMs) Synchronous reset Reset assertion in the SINC block every 32 clock cycles Current source transistors with increased W/L ratio for increased capacitance and driving power. Layout level Deep N-well isolation (NISO): The entire digital part and all the NMOS devices of the analogue part are placed inside a deep n-well to minimize digital feedthrough and latch-up susceptibility (see slide 10). P+ guard rings surround the n-channel devices to cut any possible radiation induced parasitic paths. Increased distance between the p+ diffusion in the well and the n+ in the substrate. Increased number of substrate and well contacts. AMICSA 2010, September 7 th 8

Floor-plan and fabrication highlights Polarization block Analog ring Current sources matrix 1840 um 48

Floor-plan and fabrication highlights Polarization block Analog ring Current sources matrix 1840 um 48 -lead hermetically sealed ceramic flat package Technology: 0. 13 um HCMOS 9 -GP ST-Microelectronics. TM 6 metal layers Line name: DAC 24 BISDA Dimensions: ~ 1840 x 1840 um Total area: 3. 42 mm 2 No of I/O pads: 43 Minimum pad-to-pad spacing: 90 um AMICSA 2010, September 7 th 1840 um Digital ring Digital core 9

Process AMICSA 2010, September 7 th Deep N-Well isolation (NISO) Minimizes the digital feed-through

Process AMICSA 2010, September 7 th Deep N-Well isolation (NISO) Minimizes the digital feed-through to the sensitive analog nodes Improves the latch-up immunity Layout and polarization scheme: 10

Package 48 lead hermetically sealed ceramic flat package Well proven space reliability (ST products)

Package 48 lead hermetically sealed ceramic flat package Well proven space reliability (ST products) External dimensions: (E 1 x D) 9. 65 x 15. 72 mm Die attach cavity dimensions: (L x W) 5. 58 x 3. 55 mm Bonding pad cavity dimensions: (L x W) 8. 50 x 5. 46 AMICSA 2010, September 7 th 11

Validation plan overview Functional and performance validation - characterization Static performance tests INL, DNL

Validation plan overview Functional and performance validation - characterization Static performance tests INL, DNL Offset and gain errors Power consumption Output current levels Dynamic performance tests THD+N SNR, ENOB Dynamic range DAC 24 BISDA validation Functional Radiation sensitivity tests SEE → SEU, SEL TID AMICSA 2010, September 7 th Performance Device Characterization Radiation tests 12

Validation board System block diagram Modular architecture --> Motherboard + DUT daughterboard FPGA based

Validation board System block diagram Modular architecture --> Motherboard + DUT daughterboard FPGA based design Memories UART and USART interfaces Dedicated power supplies for the DUT On-board ADC and footprint for a second DAC for performing the SEU tests. FLASH memory DUT Power Supply domains Remote keypad AMICSA 2010, September 7 th DAC Outputs (SMA) DAC DUT ADC 13

Generic test setup AMICSA 2010, September 7 th 14

Generic test setup AMICSA 2010, September 7 th 14

Validation results: Test conditions Unless otherwise noted, the following test conditions apply for all

Validation results: Test conditions Unless otherwise noted, the following test conditions apply for all the tests: Minimum: Digital power supplies VD=1. 08 V and analog power supplies VA=3. 0 V Typical: VD=1. 2 V and VA=3. 3 V Maximum: VD=1. 25 V and VA=3. 6 V Ambient temperature: Ta=25ºC Internal reference current setting resistor Rref=219 Ω f. MCLK=1. 536 MHz OSR x 256 (fs=6 k. Hz) Output load: resistive 100 Ω (1% tol. ) // 300 p. F ceramic capacitor. AMICSA 2010, September 7 th 15

Static electrical parameters summary Parameter Description Value Unit VD Digital supply voltage 1. 2

Static electrical parameters summary Parameter Description Value Unit VD Digital supply voltage 1. 2 (typ) V VA Analog supply voltage 3. 3 (typ) V PD Digital power consumption 1. 52 (typ) m. W PA Analog power consumption (normal mode) 65. 3 (typ)* m. W Pt=PA+PD Total power consumption (normal mode) 66. 8 (typ) m. W Ptdwn 2 Total power consumption (Power down 2 mode) 2. 41 (typ) m. W VBGOUT Internal reference voltage 1. 193 V Io Differential output current (per DAC) 5. 83 m. A ICM Common mode output current 2. 90 m. A ILSB Output current steered by a single CS 182 u. A Offset error 11 u. A INL Integral non-linearity 0. 5 LSB DNL Differential non-linearity 0. 5 LSB e(offset) (*) It is possible to reduce the analog power consumption by using a higher external current setting resistor Rext. AMICSA 2010, September 7 th 16

Time domain waveform Differential output DAC 1, normal mode, sine wave 100 Hz -1

Time domain waveform Differential output DAC 1, normal mode, sine wave 100 Hz -1 d. BFS AMICSA 2010, September 7 th 17

Dynamic electrical parameter summary Normal Mode, sine 100 Hz / -3 d. BFS, MBW=1

Dynamic electrical parameter summary Normal Mode, sine 100 Hz / -3 d. BFS, MBW=1 k. Hz, unbalanced output Results Dynamic range (DR): 113 d. B THD+N (SINAD): 108 d. B 110 d. B ‘bulge’ due to insufficient data AMICSA 2010, September 7 th 18

Radiation tests Preliminary radiation tests include TID and SEE (SEU, SEL) Up to now

Radiation tests Preliminary radiation tests include TID and SEE (SEU, SEL) Up to now only TID testing has been performed TID test location: Co-60 source at ESA-ESTEC, The Netherlands Dose rate setting by adjusting the distance between the DUT and the source (X) TID test setup overview X C 0 -60 facility at ESA-ESTEC AMICSA 2010, September 7 th 19

Radiation test results summary TID testing DUT sample setup Under bias conditions Constant sourcing

Radiation test results summary TID testing DUT sample setup Under bias conditions Constant sourcing of maximum output current (both DAC ON) Monitored parameters OUTP 1, OUTM 1, OUTP 2, OUTM 2, VPOL, VBGOUT, IA, ID Radiation parameters Constant dose rate: 85. 4 Rad/min Total accumulated dose: 111. 4 k. Rad (H 20) approx. 100 k. Rad (Si) Data recording sampling rate: 1 measurement / min Results No change in the value of the monitored parameters through the duration of the test. No abnormal operation observed AMICSA 2010, September 7 th 20

Conclusions and future work The cut 2. 0 has been released in order to:

Conclusions and future work The cut 2. 0 has been released in order to: include some enhancements in the digital part (serial input interface, register triplication) deduce derivatives (100 Ksamples and 1 Msamples) Perform a detailed SEU and SEL analysis The part is included in the catalog of STMicroelectronics for space application products Qualification for use in space will follow. AMICSA 2010, September 7 th 21

Thank you for your attention! Questions? AMICSA 2010, September 7 th 22

Thank you for your attention! Questions? AMICSA 2010, September 7 th 22

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