Testing Analog Digital Products Lecture 12 System Diagnosis

Testing Analog & Digital Products Lecture 12: System Diagnosis n n n Definition Functional test Diagnostic test § Fault dictionary § Diagnostic tree System design-for-testability (DFT) architecture § System partitioning § Core test-wrapper § DFT overhead Summary Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 1

A System and Its Testing n n A system is an organization of components (hardware/software parts and subsystems) with capability to perform useful functions. Functional test verifies integrity of system: § § § n Checks for presence and sanity of subsystems Checks for system specifications Executes selected (critical) functions Diagnostic test isolates faulty part: § § § For field maintenance isolates lowest replaceable unit (LRU), e. g. , a board, disc drive, or I/O subsystem For shop repair isolates shop replaceable unit (SRU), e. g. , a faulty chip on a board Diagnostic resolution is the number of suspected faulty units identified by test; fewer suspects mean higher resolution Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 2

System Test Applications Application Functional test Diagnostic test Resolution A Manufacturing Yes LRU, SRU Maintenance Yes Field repair LRU Shop repair SRU LRU: Lowest replaceable unit SRU: Shop replaceable unit Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 3

Functional Test n n All or selected (critical) operations executed with non-exhaustive data. Tests are a subset of design verification tests (testbenches). Software test metrics used: statement, branch and path coverages; provide low (~70%) structural hardware fault coverage. Examples: § § Microprocessor test – all instructions with random data (David, 1998). Instruction-set fault model – wrong instruction is executed (Thatte and Abraham, IEEETC-1980). Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 4

Gate-Level Diagnosis Karnaugh map Logic circuit (shaded squares are true outputs) b a d b c e T 2 a Stuck-at fault tests: T 1 = 010 T 2 = 011 T 3 = 100 T 4 = 110 Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 T 1 T 4 T 3 c 5

Gate Replacement Fault Karnaugh map Faulty circuit (faulty output: red sqaure is 1 output) (OR replaced by AND) a b d b c e T 2 a Stuck-at fault tests: T 1 = 010 (pass) T 2 = 011 (fail) T 3 = 100 (pass) T 4 = 110 (fail) Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 T 1 T 4 T 3 c 6

Bridging Faulty circuit Karnaugh map (OR bridge: a, c) a b c (red squares are faulty 1 outputs) b a+c d e a+c T 2 a Stuck-at fault tests: T 1 = 010 (pass) T 2 = 011 (pass) T 3 = 100 (fail) T 4 = 110 (pass) Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 T 1 T 4 T 3 c 7

Fault Dictionary Fault Test syndrome t 1 t 2 t 3 t 4 No fault 0 0 a 0, b 0, d 0 0 1 a 1 1 0 0 0 b 1 0 0 1 0 c 0 0 1 0 0 c 1, d 1, e 1 1 0 e 0 0 1 Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 a 0 : Line a stuckat-0 ti = 0, if Ti passes = 1, if Ti fails 8

Diagnosis with Dictionary look-up with minimum Hamming distance Fault OR AND OR-bridge (a, c) OR NOR Copyright 2001, Agrawal & Bushnell Test syndrome t 1 t 2 t 3 t 4 Diagnosis 0 1 e 0 0 0 1 0 b 1 1 1 Day-2 PM-3 Lecture 12 c 1, d 1, e 0 9

Diagnostic Tree T 3 T 2 Pass: t 4=0 a 1 T 3 a 1, c 1, d 1, e 1 T 4 Fail: t 4=1 c 0 T 1 T 2 a 0, b 0, d 0, e 0 Copyright 2001, Agrawal & Bushnell No fault found b 1 OR bridge (a, c) c 1, d 1, e 1 a 0, b 0, d 0 e 0 OR AND OR NOR Day-2 PM-3 Lecture 12 10

System Test: PCB vs. SOC PCB* n n n SOC** Tested parts In-circuit test (ICT) Easy test access Bulky Slow High assembly cost n n n High reliability Fast interconnects Low cost Untested cores No internal test access Mixed-signal devices * Printed circuit board ** System on a chip Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 11

Core-Based Design n Cores are predesigned and verified but untested blocks: § Soft core (synthesizable RTL) § Firm core (gate-level netlist) § Hard core (non-modifiable layout, often called legacy core) Core is the intellectual property of vendor (internal details not available to user. ) Core-vendor supplied tests must be applied to embedded cores. Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 12

Partitioning for Test n n n Partition according to test methodology: § Logic blocks § Memory blocks § Analog blocks Provide test access: § Boundary scan § Analog test bus Provide test-wrappers (also called collars) for cores. Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 13

Test-Wrapper for a Core n n Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core. Test-wrapper provides: § For each core input terminal § § § A normal mode – Core terminal driven by host chip An external test mode – Wrapper element observes core input terminal for interconnect test An internal test mode – Wrapper element controls state of core input terminal for testing the logic inside core § For each core output terminal § § § A normal mode – Host chip driven by core terminal An external test mode – Host chip is driven by wrapper element for interconnect test An internal test mode – Wrapper element observes core outputs for core test Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 14

A Test-Wrapper from/to External Test pins Scan chain to/from TAP Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 Functional core outputs Core Scan chain Functional core inputs Wrapper elements Wrapper test controller 15

Overhead of Test Access n n Test access is non-intrusive. Hardware is added to each I/O signal of block to be tested. Test access interconnects are mostly local. Hardware overhead is proportional to: (Block area) Copyright 2001, Agrawal & Bushnell – 1/2 Day-2 PM-3 Lecture 12 16

Overhead Estimate Rent’s rule: For a logic block the number of gates G and the number of terminals t are related by t = K Ga where 1 ≤ K ≤ 5, and a ~ 0. 5. Assume that block area A is proportional to G, i. e. , t is proportional to A 0. 5. Since test logic is added to each terminal t, Test logic added to terminals Overhead = ------------------------- ~ A – 0. 5 A Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 17

DFT Architecture for SOC Module N wrapper 1 Func. outputs Func. inputs Test Module wrapper Functional inputs User defined test access mechanism (TAM) Test source Test sink Functional outputs Instruction register control Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 TDO TRST TMS TCK SOC inputs Test access port (TAP) TDI Serial instruction data SOC outputs 18

DFT Components n n Test source: Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE. Test sink: Provides output verification using on-chip signature analyzer, or off-chip ATE. Test access mechanism (TAM): User-defined test data communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components. Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers. Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 19

Summary n n n Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage. Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. SOC design for testability: § § § Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries. Provide external or built-in tests for blocks. Provide test access via boundary scan and/or analog test bus. Develop interconnect tests and system functional tests. Develop diagnostic procedures. Copyright 2001, Agrawal & Bushnell Day-2 PM-3 Lecture 12 20