Systems Architecture Processor Architecture and Analysis Project 3

Systems Architecture Processor Architecture and Analysis Project 3: State Elements, Registers, and Memory Jeremy R. Johnson William M. Mongan *This lecture was derived from material in the text (Appendix B). All figures from Computer Organization and Design: The Hardware/Software Approach, Second Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED). July 2, 2001 Systems Architecture 1

Introduction • Objective: Review sequential logic and use of a clock. Provide help with Register File and Memory Unit in VHDL. • Topics – Sequential logic (elements with state) and timing (edge triggered) • Latches and flip flops • Registers – Memory • SRAM • DRAM July 2, 2001 Systems Architecture 2

Timing • Clocks used in synchronous logic – when should an element that contains state be updated? – All state elements must have the clock signal as an input • Edge-triggered timing – All state elements are updated on the same clock edge falling edge cycle time rising edge July 2, 2001 Systems Architecture 3

Edge Triggered Timing • • • State updated at clock edge read contents of some state elements, send values through some combinational logic write results to one or more state elements Clock must have sufficiently long period for combinational logic to stabilize. July 2, 2001 Systems Architecture 4

Edge Triggered Timing • Allows a state element to be used as both an input and an output July 2, 2001 Systems Architecture 5

ALU • Control Lines 000 and 001 or 010 add 110 sub 111 slt July 2, 2001 Systems Architecture 6

Determining ALU Control Bits • ALUOp determined by instruction July 2, 2001 Systems Architecture 7

ALU Control • Must describe hardware to compute 3 -bit ALU control input – given instruction type 00 = lw, sw 01 = beq, 10 = arithmetic – function code for arithmetic ALUOp computed from instruction type • Describe it using a truth table (can turn into gates): July 2, 2001 Systems Architecture 8

Datapath with Control July 2, 2001 Systems Architecture 9

Control Line Settings • 8 control lines (control read/write and multiplexors) July 2, 2001 Systems Architecture 10

Components for Simple Implementation • Functional Units needed for each instruction July 2, 2001 Systems Architecture 11

Register File • A set of registers that can be read/written by supplying a register number to be accessed. • Built using a decoder for each read and write port, and an array of D flip-flops. • For the MIPS processor, the register file has two read ports and one write port. • A write flag is used to indicate that the state should change, and a clock is needed to determine when to change state. July 2, 2001 Systems Architecture 12

Implementation of Read Ports July 2, 2001 Systems Architecture 13

Implementation of Write Ports July 2, 2001 Systems Architecture 14

Memory • Registers and register files provide the basic building blocks for small memories. • Larger memories are built from SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories) • SRAM – – 5 to 25 ns access time largest SRAMs have over 4 Million bits 4 to 6 transistors per bit value stored in cell kept on a pair of inverting gates and can be kept indefinitely • DRAM – 60 to 110 ns access time – 1 transistor per bit – charge stored in capacitor, and needs periodic refreshing July 2, 2001 Systems Architecture 15

Behavioral Model for Memory library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_arith. all; entity memory is port(address, write_data : in std_logic_vector(31 downto 0); Mem. Write, Mem. Read : in std_logic; read_data : out std_logic_vector(31 downto 0)); end memory; July 2, 2001 Systems Architecture 16

Behavioral Model for Memory architecturebehavorial of memory is type mem_array is array(0 to 7) of std_logic_vector (31 downto 0); begin mem_process: process(address, write_data) variable data_mem : mem_array : = ( to_stdlogicvector(X” 0000”), --- initialize data memory to_stdlogicvector(X” 00000000”), to_stdlogicvector(X” 00000000”), to_stdlogicvector(X” 0000”)); variable adddr : integer; July 2, 2001 Systems Architecture 17

Behavioral Model of Memory begin addr : = to_integer(address (2 downto 0)); if Mem. Write = ‘ 1’ then data_mem(addr) : = write_data; elsif Mem. Read = ‘ 1’ then read_data : = data_mem(addr) after 10 ns; end if; end process mem_process; end behavorial; July 2, 2001 Systems Architecture 18