Systems Architecture I CS 281 001 Lecture 12

Systems Architecture I (CS 281 -001) Lecture 12: Design of the MIPS ALU* Jeremy R. Johnson Mon. Nov. 13, 2000 *This lecture was derived from material in the text (sec. 4. 4 -4. 5). All figures from Computer Organization and Design: The Hardware/Software Approach, Second Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED). Nov. 13, 2000 Systems Architecture I 1

Introduction • Objective: To learn what operations are performed by the Arithmetic Logic Unit (ALU) and to learn how the MIPS ALU is implemented. • Topics – – – MIPS logical operations Full Adder 1 -But ALU The design of the MIPS 32 -Bit ALU Overflow and Overflow Detection Carry Lookahead Nov. 13, 2000 Systems Architecture I 2

Addition and Subtraction • Carry-ripple adder 0000 0111 + 0000 0110 0000 1101 0000 0111 - 0000 0110 0001 Nov. 13, 2000 0111 +1111 1010 0001 0000 0110 - 0000 0111 1111 Systems Architecture I 0000 0110 + 1111 1001 1111 3

Overflow Detection • Overflow occurs in the following situations Nov. 13, 2000 Systems Architecture I 4

Logical Operations • • Shift left << Shift right >> Shift right arithmetic Bitwise and & Bitwise or | Bitwise complement (not) ~ Exclusive or ^ Nov. 13, 2000 Systems Architecture I sll sra and, andi or, ori not (pseudo) xor, xori 5

Representation of Shift Instruction • Example sll $t 2, $s 0, 8 # $t 2 = $s 0 << 8 $t 2 = $8, $s 0 = $16 000000 10000 01010 01000 000000 op Nov. 13, 2000 rs rt rd shamt Systems Architecture I func 6

Example use of Logical Operations Int data; struct { unsigned int ready: 1; unsigned int enable: 1; unsigned int received. Byte: 8; } receiver; … data = receiver. received. Byte; receiver. ready = 0; receiver. enable = 1; Nov. 13, 2000 • Assume data in $s 0 • receiver in $s 1 9 2 1 0 | received. Byte | enable | ready • • sll $s 0, $s 1, 22 srl $s 0, 24 andi $s 1, 0 xfffe ori $s 1, 0 x 0002 Systems Architecture I 7

Building Blocks Nov. 13, 2000 Systems Architecture I 8

Full Adder • Sum = parity(a, b, Carry. In) – a xor b xor c + a b c a xor b xor c • Carry. Out = majority(a, b, Carry. In) – b Carry. In + a b Carry. In – b Carry. In + a b Carry. In a b Nov. 13, 2000 Systems Architecture I Sum 9

One-Bit ALU Nov. 13, 2000 Systems Architecture I 10

Building a 32 -Bit ALU • Chain 32 1 -Bit ALUs Nov. 13, 2000 Systems Architecture I 11

Supporting Subtraction • Subtraction is equivalent to adding the inverse – In two’s complement a + b + 1 Nov. 13, 2000 Systems Architecture I 12

Overflow and SLT • Modify last 1 -Bit ALU – SLT set if (a < b) a - b < 0 – Check sign bit after subtraction – Check overflow in last 1 -Bit ALU – Need to take overflow into account for SLT Nov. 13, 2000 Systems Architecture I 13

32 -Bit ALU with Sub and Slt Nov. 13, 2000 Systems Architecture I 14

Support Beq • a=b a-b=0 • Zero = (Result 31 + + Result 0) Nov. 13, 2000 Systems Architecture I 15

Final 32 -Bit ALU Nov. 13, 2000 Systems Architecture I 16

Carry Lookahead Adder • if (ai-1 = bi-1) then ci = 0 “kill” • if (ai-1 = bi-1) then ci = 1 “generate” • if (ai-1 bi-1) then ci = ci-1 “propagate” ci-1 ai-1 bi-1 + ci Nov. 13, 2000 Systems Architecture I 17

Combined Carry Status • xi = kill if (ai-1 = bi-1) • xi = generate if (ai-1 = bi-1) • xi = propagate if (ai-1 bi-1) FAi-1 • yi = yi-1 xi = x 1 xi Nov. 13, 2000 Systems Architecture I 18

Calculating Carry from Carry Status Lemma: – yi = kill ci = 0 – yi = generate ci = 1 – yi = propagate does not occur Proof: 1 yi = kill xi = kill ci = 0 or – xi = propagate and yi-1 = kill and ci = majority(ci-1, ai, bi) = ci-1 = kill (by induction) 2 yi = generate xi = generate ci = 1 or – xi = propagate and yi-1 = generate and ci = majority(ci-1, ai, bi) = 1 (by induction) 3 yi = propagate xi = propagate and yi-1 = propagate, which by induction leads to a contradiction Nov. 13, 2000 Systems Architecture I 19

Parallel Prefix • Fast (parallel computation of yi in log time) x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 [0, 1] [1, 2] [2, 3] [3, 4] [4, 5] [5, 6] [6, 7] [0, 2] [0, 3] [1, 4] [2, 5] [3, 6] [4, 7] [0, 0] [0, 1] [0, 2] [0, 3] [0, 4] [0, 5] [0, 6] [0, 7] Nov. 13, 2000 Systems Architecture I 20

Parallel Prefix Nov. 13, 2000 Systems Architecture I 21