Sequential Circuit BIST Synthesis using Spectrum and Noise
Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, Alabama 36849, USA November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 1
Outline Specifying a BIST problem l Proposed method l l Results l l l Spectral Analysis BIST implementation Fault Coverage Area Overhead Conclusion November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 2
Two Types of BIST methods l Scan-based testing l l l Advantages: l High fault coverage Disadvantages: l Area & delay overhead, yield loss, large vector size and testing times Non-scan based testing l l Advantages: l Disadvantages of scan-based testing eliminated Disadvantages: l Requires sequential ATPG § l November 25 High test generation complexity and low fault coverages § Alleviated using DFT schemes Problem definition Sequential ATPG-like vector generation in BIST environment Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 3
Proposed Method l Step 1: Spectral analysis l l l Sequential vectors (ATPG or any other type) analyzed in the spectral domain Significant spectral components chosen for BIST implementation Step 2: BIST implementation l Hardware synthesis of significant spectral components to generate ATPG-like vectors November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 4
Test vectors and bit-streams Outputs . . Vector K November 25 → . . . Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan A bit-stream Time Vector 1 → Vector 2 → Vector 3 → Vector 4 → Vector 5 → Input J Input 5 Input 4 Input 3 Input 2 Input 1 Sequential Circuit (CUT) 5
Spectral Characterization of a Bit-Stream w 0 Walsh functions (order 8) w 1 w 2 Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit-stream • Walsh functions form the rows of a Hadamard matrix • w 3 H 8 = 1 1 1 1 1 -1 1 1 -1 -1 1 -1 -1 1 1 1 -1 -1 1 1 -1 w 4 w 5 w 6 w 7 time November 25 Example of Hadamard matrix of order 8 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 6
. . . Input 2 Input 1 Analyzing Bit-Streams of ATPG vectors Set 1 Vector 2. . . Spectral coeffs. Bit stream Spectral Analysis 0 s to -1 s Set j Time Sets of bit-streams of Input 2 November 25 . . input 2 set 1 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan C(2, 1) input 2 set 1 7
Determining Significant Components For input i Component Spectrum Set 1 . . Averaged Spectrums Set J Averaging . . Power Spectrum Phases of significant components Averaging . . M significant components chosen November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 8
Input Vector Holding l l l Hold input vectors constant while applying system clock. Holding length related to sequential depth. Sequential depth: Maximum number of FFs on any path between PI and PO. Holding a vector constant for number of clock cycles equal to sequential depth propagates a fault through the activated sequential path[1]. Holding maps combinational ATPG onto acyclic sequential circuit [2]. However, all testable combinational ATPG faults not detected by holding [3]. [1] L. Nachman, K. Saluja, S. Upadyaya, and R. Reuse, “Random Pattern Testing for Sequential Circuits Revisited, ” in Proc. Fault. Tolerant Computing Symp. , pp. 44– 52, June 1996. [2] H. B. Min and W. A. Rogers, “A Test Methodology for Finite State Machines using Partial Scan Design, ” J. Electronic Testing: Theory and Applications, vol. 3, no. 2, pp. 127– 137, 1992. [3] Y. C. Kim, V. D. Agrawal, and K. K. Saluja, "Combinational Automatic Test Pattern Generation for Acyclic Sequential Circuits, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 6, pp. 948 -956, June 2005. November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 9
Holding and Weighted Random Patterns Number of faults detected Circuit Total No. of faults 64 k random vectors Without holding With holding 64 k weighted random vectors Without holding With holding s 298 308 269 273 273 s 820 850 414 449 744 764 s 1423 1515 891 1217 1449 1469 s 1488 1486 1161 1369 1443 s 5378 4603 3222 3424 3288 3537 s 9234 6927 1268 1305 1293 1303 s 15850 13863 5249 6270 5847 6696 s 38417 31180 4087 4185 4803 4949 November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 10
BIST Architecture M-bit counter divides system clock frequency repeatedly by 2 and generates BIST clock System clock Clock divider and holding circuit N-bit counter with XOR gates BIST clock Hadamard wave generator Weighted random bit-stream (W=0. 5) Bit-stream(W=0. 5) of spectral To. Noise Proportion: inserted bit component CUT SC 1 = 0. 5 -stream SC 1 SC 2 = 0. 5 Proportion: Weighted random SC 1 = 0. 25 SC 2 bit-stream (W = 0. 25) SC 2 = 0. 25 SC 3 = 0. 5 SC 3 Cellular Automata Register with AND-OR gates Weighted pseudo-random pattern generator 2 System clock 3 BIST clock 1 Hadamard Components 1 Spectral component synthesizer Input 2 Randomizer 1 Weighted pseudo-random bit-streams November 25 Input 1 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan To CUT Input 3 11
Hadamard BIST Results Number of faults detected Circuit Total No. of faults Flex Test ATPG 64 k random vectors 64 k weighted random vectors Hadamard Haar BIST 1 BIST (64 k vectors) s 298 308 273 273 273 s 820 850 793 449 764 777 710 s 1423 1515 1443 1217 1469 1468 s 1488 1486 1446 1369 1443 1441 s 5378 4603 3547 3424 3537 3603 3609 s 9234 6927 1588 1305 1303 1729 1413 s 15850 13863 7323 6270 6696 6844 5888 s 38417 31180 15472 4185 4949 17020 4244 Equal or more faults 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using detected than ATPG in and Correlation for Sequential BIST, ” in Modulation by Haar Wavelets Proc. International Conf. VLSI Design, 2007, pp. 485– 491. 5 /20 th 8 circuits November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 12
Hadamard BIST Results Number of faults detected Circuit Total No. of faults Flex Test ATPG 64 k random vectors 64 k weighted random vectors Hadamard Haar BIST 1 BIST (64 k vectors) s 298 308 273 273 273 s 820 850 793 449 764 777 710 s 1423 1515 1443 1217 1469 1468 s 1488 1486 1446 1369 1443 1441 s 5378 4603 3547 3424 3537 3603 3609 s 9234 6927 1588 1305 1303 1729 1413 s 15850 13863 7323 6270 6696 6844 5888 s 38417 31180 15472 4185 4949 17020 4244 November 25 Maximum faults detected in Asian Test Symposium 2008, Nov 24 -27, Sapporo, 6 /Japan 8 circuits 13
Longer BIST Sequences Flex. Test Circuit Fault coverage (%) Hadamard BIST No. of vectors Fault coverage (%) at 64 K vectors Fault coverage (%) at 128 K vectors BIST vecs. for Flex. Test ATPG cov. s 298 88. 64 153 88. 64 757 s 820 93. 29 1127 91. 41 91. 88 (!) s 1423 95. 25 3882 96. 90 22345 s 1488 97. 31 736 97. 11 (!) s 5378 77. 06 739 78. 27 78. 67 8984 s 9234 22. 92 15528 24. 96 25. 25 8835 s 15850 52. 82 61687 49. 37 52. 15 198061 s 38417 49. 62 55110 54. 59 63. 07 43240 November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan ATPG fault coverage 14 achieved in 6 / 8 circuits
Area Overhead Circuit No. of transistors in circuit Hadamard BIST No. of transistors % Area overhead Haar BIST 1 No. of transistors % Area overhead s 298 890 908 102. 02 834 93. 71 s 820 1896 1472 77. 64 1612 85. 02 s 1423 4624 1637 35. 40 1555 33. 63 s 1488 4006 1069 26. 68 1078 26. 91 s 5378 12840 2342 18. 24 2487 19. 37 s 9234 23356 2700 11. 56 2552 10. 93 s 15850 43696 4908 11. 23 4595 10. 52 s 38417 108808 3606 3. 31 2135 1. 96 Approximately similar area overheads 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST, ” in Proc. 20 th International Conf. VLSI Design, 2007, pp. 485– 491. November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 15
Conclusion l l l Proposed a novel method for test generation for sequential circuit BIST l Proposed unique circuits for mixing spectral components and noise l Method detects equal or more faults than ATPG vectors in 6 out of 8 ISCAS’ 89 benchmark circuits l Moderate area overhead compared to existing methods Proposed method is flexible and adaptable l Any other suitable vectors can be used instead of ATPG vectors. l Any compatible transform for binary bit-streams can be used for spectral analysis instead of Hadamard transform. BIST coverage limited by coverage of ATPG vectors l DFT for sequential circuits to improve ATPG coverage November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 16
Thank You! Any questions please ? November 25 Asian Test Symposium 2008, Nov 24 -27, Sapporo, Japan 17
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