Sequential Circuit BIST Synthesis using Spectrum and Noise

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Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi and

Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, AL 36849 1

BIST Methods n Scan-based testing q Advantages: n q Disadvantages: n n High fault

BIST Methods n Scan-based testing q Advantages: n q Disadvantages: n n High fault coverage Area & delay overhead, yield loss, large vector size and testing times Non-scan based testing q Advantages: n q Disadvantages of scan-based testing eliminated Disadvantages: n Requires sequential ATPG q n High test generation complexity and low fault coverages § Alleviated using DFT schemes Nontrivial vector generation in BIST environment Problem definition 2

Proposed Method n Step 1: Spectral Analysis q q n ATPG vectors analyzed in

Proposed Method n Step 1: Spectral Analysis q q n ATPG vectors analyzed in the spectral domain Prominent spectral components chosen for BIST implementation Step 2: BIST implementation q Prominent spectral components combined to generate ATPG-like vectors. 3

Spectral Characterization of Bit-Streams w 0 Walsh functions (order 8) w 1 w 2

Spectral Characterization of Bit-Streams w 0 Walsh functions (order 8) w 1 w 2 • Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit-stream. • Walsh functions form the rows of a Hadamard matrix. w 3 H 8 = 1 1 1 1 1 -1 1 1 -1 -1 1 -1 -1 1 1 1 -1 -1 1 1 -1 w 4 w 5 w 6 w 7 time Example of Hadamard matrix of order 8 4

. . . Input 2 Input 1 Analyzing Bit-Streams of ATPG vectors Vector 1

. . . Input 2 Input 1 Analyzing Bit-Streams of ATPG vectors Vector 1 Vector 2. . . Spectral coeffs. Bit stream Spectral Analysis 0 s to -1 s Bit-stream of Input 2 . . Input 2 Set 1 C(i, j) i th input j th set 5

Determining Prominent Components For input i Component Spectrum Set 1 . . Averaged Spectrums

Determining Prominent Components For input i Component Spectrum Set 1 . . Averaged Spectrums Set J Averaging . . Power Spectrum Phases of prominent components Averaging . . M prominent components chosen 6

BIST Architecture System clock Clock divider N-bit counter with XOR gates Clock derived signals

BIST Architecture System clock Clock divider N-bit counter with XOR gates Clock derived signals 2 Set Weighted M-bit counter. Length which divides random bit-stream the clock Clock frequency bit-stream (W=0. 5) Bit-stream System repeatedly by 2 Holder BIST clock Hadamard wave generator of spectral Clock Proportion: component SC 1 = 0. 5 SC 1 Hold SC 2 = 0. 5 Clock Weighted random SC 2 bit-stream (W = 0. 25) SC 3 Noise BISTbit inserted Clock -stream Proportion: SC 1 = 0. 25 SC 2 = 0. 25 SC 3 = 0. 5 Cellular Automata Register with AND-OR gates Weighted pseudo-random pattern generator 2 System clock 3 BIST clock 1 Hadamard Components Weighted pseudo-random bit-streams 1 Spectral component synthesizer Input 1 Input 2 Randomizer 1 To CUT Input 3 7

Hadamard BIST Results Number of faults detected Circuit Total No. of faults Flex Test

Hadamard BIST Results Number of faults detected Circuit Total No. of faults Flex Test ATPG Random (64 k vectors) Weighted Random (64 k) Without holding Without Holding With Holding Hadamard BIST (64 k) Haar BIST 1 (64 k) s 298 308 273 269 273 273 273 s 820 850 793 414 449 744 764 777 710 s 1423 1515 1443 891 1217 1449 1468 s 1488 1486 1446 1161 1369 1443 1441 s 5378 4603 3547 3222 3424 3288 3537 3603 3609 s 9234 6927 1588 1268 1305 1293 1303 1729 1413 s 15850 13863 7323 5249 6270 5847 6696 6844 5888 s 38417 31180 15472 4087 4185 4803 4949 17020 4244 Equal Maximum or more faults detected thanin. ATPG in 6 5/ 8/ 8 circuits 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST, ” in Proc. 20 th International Conf. VLSI Design, 2007, pp. 485– 491. 8

Hadamard Results Flex. Test Circuit Fault Cov. (%) Hadamard BIST No. of vectors Fault

Hadamard Results Flex. Test Circuit Fault Cov. (%) Hadamard BIST No. of vectors Fault coverage (%) at 64 K vecs. Fault coverage (%) at 128 K vecs. BIST vecs. for Flex. Test ATPG cov. s 298 88. 64 153 88. 64 757 s 820 93. 29 1127 91. 41 91. 88 (!) s 1423 95. 25 3882 96. 90 22345 s 1488 97. 31 736 97. 11 (!) s 5378 77. 06 739 78. 27 78. 67 8984 s 9234 22. 92 15528 24. 96 25. 25 8835 s 15850 52. 82 61687 49. 37 52. 15 198061 s 38417 49. 62 55110 54. 59 63. 07 43240 Equal or more faults detected than ATPG in 6 / 8 circuits 9

Area Overhead Circuit No. of trans. in circuit Hadamard BIST With clock divider circuit

Area Overhead Circuit No. of trans. in circuit Hadamard BIST With clock divider circuit No. of trans. % Area overhead Haar BIST 1 Without clock divider circuit No. of trans. % Area overhead s 298 890 908 102. 02 820 92. 13 834 93. 71 s 820 1896 1472 77. 64 1340 70. 68 1612 85. 02 s 1423 4624 1637 35. 40 1483 32. 07 1555 33. 63 s 1488 4006 1069 26. 68 959 23. 94 1078 26. 91 s 5378 12840 2342 18. 24 2210 17. 21 2487 19. 37 s 9234 23356 2700 11. 56 2502 10. 71 2552 10. 93 s 15850 43696 4908 11. 23 4666 10. 68 4595 10. 52 s 38417 108808 3606 3. 31 3364 3. 09 2135 1. 96 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST, ” in Proc. 20 th International Conf. VLSI Design, 2007, pp. 485– 491. 10

Testability analysis and enhancement n Improving testability q q n RTL faults 2 defined

Testability analysis and enhancement n Improving testability q q n RTL faults 2 defined as faults on the boundary of combinational logic XOR tree connecting unobservable RTL faults Identifying untestability q Sequentially untestable faults identified usingle fault theorem 3 2. N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Gate-Level Stuck-at Faults, ” in Proc. 15 th IEEE Asian Test Symp. , 2006, pp. 83– 88. 3. V. D. Agrawal and S. T. Chakradhar, “Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits, ” IEEE Trans. Computer-Aided Design, vol. 14, no. 9, pp. 1155– 1160, Sept. 1995. 11

Fault and Test Coverages n n n Example circuit: s 5378 XOR tree inserted

Fault and Test Coverages n n n Example circuit: s 5378 XOR tree inserted to observe outputs of 49 flip-flops from a total of 179 683 faults found as sequentially untestable usingle fault theorem 3 Test Method Fault Coverage (%) Test Coverage (%) Without DFT With DFT Flex. Test ATPG 77. 05 82. 22 92. 80 96. 55 Hadamard BIST 78. 27 81. 23 94. 27 95. 38 3. V. D. Agrawal and S. T. Chakradhar, “Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits, ” IEEE Trans. Computer-Aided Design, vol. 14, no. 9, pp. 1155– 1160, Sept. 1995. 12

Conclusion n Proposed a novel method for test generation for sequential circuit BIST q

Conclusion n Proposed a novel method for test generation for sequential circuit BIST q Proposed unique circuits for mixing spectral components and noise q Method detects equal or more faults than ATPG vectors in 6 out of 8 ISCAS’ 89 benchmark circuits q Moderate area overhead compared to existing methods n Performed testability analysis and enhancement on an example circuit i. e. s 5378 n Proposed method is flexible and adaptable q Any other suitable vectors can be used instead of ATPG vectors. q Any compatible transform for binary transforms can be used for spectral analysis instead of Hadamard transform. 13

Thank You! Any questions please ? 14

Thank You! Any questions please ? 14