Paging CS502 Operating Systems Fall 2009 EMC Slides

Paging CS-502, Operating Systems Fall 2009 (EMC) (Slides include materials from Modern Operating Systems, 3 rd ed. , by Andrew Tanenbaum and from Operating System Concepts, 7 th ed. , by Silbershatz, Galvin, & Gagne) CS-502 (EMC) Fall 2009 Paging 1

Review – Memory Management • Allocation of physical memory to processes • Virtual Address • Address space in which the process “thinks” • Each virtual address is translated “on the fly” to a physical address • Fragmentation • Internal fragmentation – unused within an allocation • External fragmentation – unused between allocations CS-502 (EMC) Fall 2009 Paging 2

Review – Memory Management (cont’d) • Segmentation • Recognition of different parts of virtual address space • Different allocation strategies • The rule of “no free lunch” • Fixed size allocations no external fragmentation, more internal fragmentation • Variable allocations no internal fragmentation, more external fragmentation CS-502 (EMC) Fall 2009 Paging 3

Reading Assignment • Tanenbaum – §§ 3. 1 -3. 2 (previous topic – Memory Management) – § 3. 3 (this topic on Paging) CS-502 (EMC) Fall 2009 Paging 4

Paging • A different approach • Addresses all of the issues of previous topic • Introduces new issues of its own CS-502 (EMC) Fall 2009 Paging 5

Memory Management • Virtual (or logical) address vs. Physical address • Memory Management Unit (MMU) – Set of registers and mechanisms to translate virtual addresses to physical addresses • Processes (and processors) see virtual addresses – Virtual address space is same for all processes, usually 0 based – Virtual address spaces are protected from other processes Processor Logical Addresses MMU Physical Addresses Memory I/O Devices • MMU and devices see physical addresses CS-502 (EMC) Fall 2009 Paging 6

Paging CS-502 (EMC) Fall 2009 Paging 7 physical memory frame 0 frame 1 frame 2 … … • Use small fixed size units in both physical and Logical Address Space virtual memory (virtual memory) • Provide sufficient MMU page 0 hardware to allow page 1 units to be scattered across memory page 2 • Make it possible to leave MMU page 3 infrequently used parts of virtual address space out page X of physical memory • Solve internal & external fragmentation problems frame Y

Paging • Processes see a large virtual address space • Either contiguous or segmented • Memory Manager divides the virtual address space into equal sized pieces called pages • Some systems support more than one page size • Memory Manager divides the physical address space into equal sized pieces called frames – Size usually a power of 2 between 512 and 8192 bytes – Some modern systems support 64 megabyte pages! – Frame table • One entry per frame of physical memory; each entry is either – Free – Allocated to one or more processes • sizeof(page) = sizeof(frame) CS-502 (EMC) Fall 2009 Paging 8

Address Translation for Paging • Translating virtual addresses – a virtual address has two parts: virtual page number & offset – virtual page number (VPN) is index into a page table – page table entry contains page frame number (PFN) – physical address is: startof(PFN) + offset • Page tables – Supported by MMU hardware – Managed by the Memory Manager – Map virtual page numbers to page frame numbers • one page table entry (PTE) per page in virtual address space • i. e. , one PTE per VPN CS-502 (EMC) Fall 2009 Paging 9

Paging Translation logical address virtual page # offset physical memory page frame 0 page frame 1 page frame 2 page frame 3 page table physical address F(PFN) offset … page frame # page frame Y CS-502 (EMC) Fall 2009 Paging 10

Page Translation Example • Assume a 32 -bit contiguous address space – Assume page size 4 KBytes (log 2(4096) = 12 bits) – For a process to address the full logical address space • Need 220 PTEs – VPN is 20 bits • Offset is 12 bits • Translation of virtual address 0 x 12345678 – Offset is 0 x 678 – Assume PTE(0 x 12345) contains 0 x 01010 – Physical address is 0 x 01010678 CS-502 (EMC) Fall 2009 Paging 11

Generic PTE Structure 1 1 1 2 V R M prot 20 page frame number • Valid bit gives state of this Page Table Entry (PTE) – says whether or not its virtual address is valid – in memory and VA range – If not set, page might not be in memory or may not even exist! • Reference bit says whether the page has been accessed – it is set by hardware whenever a page has been read or written to • Modify bit says whether or not the page is dirty – it is set by hardware during every write to the page • Protection bits control which operations are allowed – read, write, execute, etc. • Page frame number (PFN) determines the physical page – physical page start address • Other bits dependent upon machine architecture CS-502 (EMC) Fall 2009 Paging 12

Paging – Advantages • Easy to allocate physical memory • pick any free frame • No external fragmentation • All frames are equal • Minimal internal fragmentation • Bounded by page/frame size • Easy to swap out pages (called pageout) • Size is usually a multiple of disk blocks • PTEs may contain info that help reduce disk traffic • Processes can run with not all pages swapped in CS-502 (EMC) Fall 2009 Paging 13

Definition — Page Fault • Trap when process attempts to reference a virtual address in a page with Valid bit in PTE set to false • E. g. , page not in physical memory • If page exists on disk: – • Suspend process • If necessary, throw out some other page (& update its PTE) • Swap in desired page, resume execution • If page does not exist on disk: – • Return program error or • Conjure up a new page and resume execution – E. g. , for growing the stack! CS-502 (EMC) Fall 2009 Paging 14

Steps in Handling a Page Fault CS-502 (EMC) Fall 2009 Paging 15

Definition — Backing Storage • A place on external storage medium where copies of virtual pages are kept • Usually a hard disk (locally or on a server) • Place from which contents of pages are read after page faults • Place where contents of pages are written if page frames need to be re-allocated CS-502 (EMC) Fall 2009 Paging 16

Backing Storage • Executable code and constants: – • The loadable image file produced by compiler • Working memory (stack, heap, static data) • Special swapping file (or partition) on disk • Persistent application data • Application data files on local or server disks CS-502 (EMC) Fall 2009 Paging 17

Requirement for Paging to Work! • Machine instructions must be capable of restarting • If execution was interrupted during a partially completed instruction, need to be able to – continue or – redo without harm • This is a property of all modern CPUs … – … but not of some older CPUs! CS-502 (EMC) Fall 2009 Paging 18

Note • Protection bits are important part of paging • A process may have valid pages that are • not writable • execute only • etc. • E. g. , setting PTE protection bits to prohibit certain actions is a legitimate way of detecting the first action to that page. CS-502 (EMC) Fall 2009 Paging 19

Example • A page may be logically writable, as required by the application, but … • … setting PTE bits to disallow writing is a way of detecting the first attempt to write • Take some action • Reset PTE bit • Allow process to continue as if nothing happened CS-502 (EMC) Fall 2009 Paging 20

Questions? CS-502 (EMC) Fall 2009 Paging 21

Observations • Recurring themes in paging – Temporal Locality – locations referenced recently tend to be referenced again soon – Spatial Locality – locations near recent references tend to be referenced soon • Definitions – Working set: The set of pages that a process needs to run without frequent page faults – Thrashing: Excessive page faulting due to insufficient frames to support working set CS-502 (EMC) Fall 2009 Paging 22

Paging Issues • #1 — Page Tables can consume large amounts of space – If PTE is 4 bytes, and use 4 KB pages, and have 32 bit VA space 4 MB for each process’s page table • Stored in main memory! – What happens for 64 -bit logical address spaces? • #2 — Performance Impact – Converting virtual to physical address requires multiple operations to access memory • • Read Page Table Entry from memory! Get page frame number Construct physical address Assorted protection and valid checks – Without fast hardware support, requires multiple memory accesses and a lot of work per logical address CS-502 (EMC) Fall 2009 Paging 23

Issue #1: Page Table Size • Process Virtual Address spaces – Not usually full – don’t need every PTE – Processes do exhibit locality – only need a subset of the PTEs • Two-level page tables • I. e. , Virtual Addresses have 3 parts – Master page number – points to secondary page table – Secondary page number – points to PTE containing page frame # – Offset • Physical Address = offset + startof (PFN) CS-502 (EMC) Fall 2009 Paging 24

Two-level page tables virtual address master page # secondary page# offset physical memory master page table physical address page frame # secondary page table # addr page frame 0 page frame 1 offset secondary page table # page frame 2 page frame 3 … page frame number page frame Y CS-502 (EMC) Fall 2009 Paging 25

Two-level page tables 12 bits 8 bits 12 bits virtual address master page # secondary page# offset physical memory master page table physical address page frame # secondary page table # addr page frame 0 page frame 1 offset secondary page table # page frame 2 page frame 3 … page frame number page frame Y CS-502 (EMC) Fall 2009 Paging 26

Note • Note: Master page number can function as Segment number – previous topic • n-level page tables are possible, but rare in 32 -bit systems CS-502 (EMC) Fall 2009 Paging 27

Multilevel Page Tables • Sparse Virtual Address space – very few secondary PTs ever needed • Process Locality – only a few secondary PTs needed at one time • Can page out secondary PTs that are not needed now – Don’t page Master Page Table – Save physical memory However • Performance is worse – Now have 3 (or more) memory accesses per virtual memory reference or instruction fetch • How do we get back to about 1 memory access per VA reference? – Problem #2 of “Paging Issues” slide CS-502 (EMC) Fall 2009 Paging 28

Paging Issues • Minor issue – internal fragmentation – Memory allocation in units of pages (also file allocation!) • #1 — Page Tables can consume large amounts of space – If PTE is 4 bytes, and use 4 KB pages, and have 32 bit VA space -> 4 MB for each process’s page table – What happens for 64 -bit logical address spaces? • #2 — Performance Impact – Converting virtual to physical address requires multiple operations to access memory • • Read Page Table Entry from memory! Get page frame number Construct physical address Assorted protection and valid checks – Without fast hardware, requires multiple memory accesses and a lot of work per logical address CS-502 (EMC) Fall 2009 Paging 29

Solution — Associative Memory aka Dynamic Address Translation — DAT aka Translation Lookaside Buffer — TLB VPN # • • • PTE Do fast hardware search of all entries in parallel for VPN If present, use page frame number from PTE directly If not, a) Look up in page table (multiple accesses) b) Load VPN and PTE into Associative Memory (throwing out another entry as needed) CS-502 (EMC) Fall 2009 Paging 30

Translation Lookaside Buffer (TLB) • Associative memory implementation in hardware – Translates VPN to PTE (containing PFN) – Done in single machine cycle • TLB is hardware assist – Fully or partially associative – entries searched in parallel with VPN as index – Returns page frame number (PFN) – MMU use PFN and offset to get Physical Address • Locality makes TLBs work – Usually have 8– 1024 TLB entries – Sufficient to deliver 99%+ hit rate (in most cases) • Works well with multi-level page tables CS-502 (EMC) Fall 2009 Paging 31

MMU with TLB CS-502 (EMC) Fall 2009 Paging 32

Typical Machine Architecture Memory I/O device CS-502 (EMC) Fall 2009 CPU MMU and TLB live here Bridge Graphics I/O device Paging I/O device 33

TLB-related Policies • OS must ensure that TLB and page tables are consistent – When OS changes bits (e. g. protection) in PTE, it must invalidate TLB copy – Dirty bit and reference bits in TLB must be written back to PTE • TLB replacement policies – Random – Least Recently Used (LRU) – with hardware help • What happens on context switch? – – Each process has own page tables (possibly multi-level) Must invalidate all TLB entries Then TLB fills up again as new process executes Expensive context switches just got more expensive! • Note benefit of Threads sharing same address space CS-502 (EMC) Fall 2009 Paging 34

Questions? CS-502 (EMC) Fall 2009 Paging 35

Alternative Page Table format – Hashed • Common in address spaces > 32 bits. • The virtual page number is hashed into a page table. • Each entry contains a chain of VPN’s with same hash. • Search chain for match • If found, use associated PTE • Still needs TLB for performance CS-502 (EMC) Fall 2009 Paging 36

Hashed Page Tables CS-502 (EMC) Fall 2009 Paging 37

Alternative Page Table format – Inverted • One entry for each real page of memory. • Entry consists of virtual address of page stored at that real memory location, with information about the process that owns that page. • Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs. • Use hash table to limit the search to one or a few page-table entries. • Still uses TLB to speed up execution CS-502 (EMC) Fall 2009 Paging 38

Inverted Page Table Architecture See also Tanenbaum, Fig 3 -14 CS-502 (EMC) Fall 2009 Paging 39

Inverted Page Table Architecture (cont’d) • Apollo Domain systems • Common in 64 -bit address systems • Supported by TLB • Next topic helps to quantify size of TLB CS-502 (EMC) Fall 2009 Paging 40

Paging – Some Tricks • Shared Memory – Part of virtual memory of two or more processes map to same frames • Finer grained sharing than segments • Data sharing with Read/Write • Shared libraries with e. Xecute – Each process has own PTEs – different privileges CS-502 (EMC) Fall 2009 Paging 41

Shared Pages (illustration) CS-502 (EMC) Fall 2009 Paging 42

Paging trick – Copy-on-write (COW) • During fork() – Don’t copy individual pages of virtual memory – Just copy page tables; all pages start out shared – Set all PTEs to read-only in both processes • When either process hits a write-protection fault on a valid page – Make a copy of that page, set write protect bit in PTE to allow writing – Resume faulting process • Saves a lot of unnecessary copying – Especially if child process will delete and reload all of virtual memory with call to exec() CS-502 (EMC) Fall 2009 Paging 43

Definition — Mapping • Mapping (a part of) virtual memory to a file = • Connecting blocks of the file to the virtual memory pages so that – Page faults in (that part of) virtual memory resolve to the blocks of the file – Dirty pages in (that part of) virtual memory are written back to the blocks of the file CS-502 (EMC) Fall 2009 Paging 44

Warning — Memory-mapped Files • Tempting idea: – – Instead of standard I/O calls (read(), write(), etc. ) map file starting at virtual address X – Access to “X + n” refers to file at offset n – Use paging mechanism to read file blocks into physical memory on demand … en mance v e ; or m f a r r e – … and write them out as neededto prog anage p d Har er to m times Hard • Has been tried many • Rarely works well in practice CS-502 (EMC) Fall 2009 Paging 45

an m c Fro r topi lie r a e Virtual Memory Organization 0 x. FFFF stack (dynamically allocated) SP Virtual address space heap (dynamically allocated) static data 0 x 0000 CS-502 (EMC) Fall 2009 program code (text) Paging PC 46

Virtual Memory Organization Map to writable swap file Unmapped, may be dynamically mapped stack (dynamically allocated) SP guard page (never mapped) Map to writable swap file heap (dynamically allocated) Map to writable swap file static data Mapped to read-only executable file CS-502 (EMC) Fall 2009 program code & constants Paging PC 47

Virtual Memory Organization (continued) thread 1 stack Map to writable swap file SP (T 1) guard page thread 2 stack SP (T 2) guard page thread 3 stack Unmapped, may be dynamically mapped guard page (never mapped) heap Map to writable swap file Mapped to read-only executable file CS-502 (EMC) Fall 2009 SP (T 3) static data PC (T 2) program code & constants Paging PC (T 3) 48

Virtual Memory Organization (continued) • Each area of process VM is its own segment (or sequence of segments) • Executable code & constants – fixed size • Shared libraries • Static data – fixed size • Heap – open-ended • Stacks – each open-ended • Other segments as needed – E. g. , symbol tables, loader information, etc. CS-502 (EMC) Fall 2009 Paging 49

Virtual Memory – a Major OS Abstraction • Processes execute in virtual memory, not physical memory • Virtual memory may be very large • Much larger than physical memory • Virtual memory may be organized in interesting & useful ways • Open-ended segments • Virtual memory is where the action is! • Physical memory is just a cache of virtual memory CS-502 (EMC) Fall 2009 Paging 50

Reading Assignment • Tanenbaum – §§ 3. 1 -3. 2 (previous topic – Memory Management) – § 3. 3 (this topic on Paging) CS-502 (EMC) Fall 2009 Paging 51

Related topic – Caching CS-502 (EMC) Fall 2009 Paging 52

Definition — Cache • A small subset of active items held in fast storage while most of the items are in much larger, slower storage – Virtual Memory • Very large, mostly stored on (slow) disk • Small working set in (fast) RAM during execution – Page tables • Very large, mostly stored in (slow) RAM • Small working set stored in (fast) TLB registers CS-502 (EMC) Fall 2009 Paging 53

Caching is Ubiquitous in Computing • Transaction processing • Keep records of today’s departures in RAM while records of future flights are on disk • Program execution • Keep the bytes near the current program counter in on-chip memory while rest of program is in RAM • File management • Keep disk maps of open files in RAM while retaining maps of all files on disk • Game design • Keep nearby environment in cache of each character • … CS-502 (EMC) Fall 2009 Paging 54

Caching issues • When to put something in the cache • What to throw out to create cache space for new items • How to keep cached item and stored item in sync after one or the other is updated • How to keep multiple caches in sync across processors or machines • Size of cache needed to be effective • Size of cache items for efficiency • … CS-502 (EMC) Fall 2009 Paging 55

y r e v t! a s i is l s i t Th ortan imp Caching issues • When to put something in the cache • What to throw out to create cache space for new items • How to keep cached item and stored item in sync after one or the other is updated • How to keep multiple caches in sync across processors or machines • Size of cache needed to be effective • Size of cache items for efficiency • … CS-502 (EMC) Fall 2009 Paging 56

Questions? CS-502 (EMC) Fall 2009 Paging 57