EMC Guidelines EMC guidelines EMC should be taken

EMC Guidelines

EMC guidelines EMC should be taken into account at early design stage… K. Armstrong, Advanced PCB design and layout for EMC 2 September 21

EMC guidelines Which problems? Know your enemy Power integrity (PI) Signal integrity (SI) ESD, EFT, EOS Radiated immunity (RI) Conducted emission (CE) Integrated circuits / electronic applications Conducted immunity (CI) 3 September 21 Radiated emission (RE)

Summary 1. Golden Rules for low emission • Power supply routing strategy • Decoupling capacitance • Reduction of core noise • Reduction of IO noise 2. Golden Rules for low susceptibility • Decoupling capacitance • Reduce rectification issues in analog circuits • Isolation of Noisy blocks • Improve noise immunity of IOs 4 September 21

Golden Rules for Low Emission Rule 1: Power supply routing strategy A) Use shortest interconnection to reduce the serial inductance • • • Inductance is a major source of resonance Each conductor acts as an inductance Ground plane modifies inductance value (worst case is far from groun Reducing inductance decreases SSN !! Lead: L=0. 6 n. H/mm Bonding: L=1 n. H/mm 5 September 21

Golden Rules for Low Emission Rule 1: Power supply routing strategy A) Use shortest interconnection to reduce the serial inductance Leadframe package: L up to 10 n. H Die of the IC Long leads bondin g Far from ground PCB Shor t leads Flip chip package: L up to 3 n. H Die of the IC balls Close from ground Requirements for high speed microprocessors : L < 50 p. H ! 6 September 21

Golden Rules for Low Emission Rule 1: Power supply routing strategy A) Use double/triple bonding on pins with large di/dt 7 September 21

Golden Rules for Low Emission Rule 1: Power supply routing strategy B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs 9 I/O ports Fail Correct 8 September 21

Golden Rules for Low Emission Rule 1: Power supply routing strategy C) Place supply pairs close to noisy blocks Current density simulation Layout view Memory PLL Digital core VDD / VSS 9 September 21

Golden Rules for Low Emission Rule 1: Power supply routing strategy D) Place VSS and VDD pins as close as possible • to increase decoupling capacitance that reduces fluctuations • to reduce current loops that provoke magnetic field Added contribution s current Lea d Die Current loop Reduced contributions EM wave EM field current Lead currents 10 September 21

Golden Rules for Low Emission Rule 1: Power supply routing strategy Case study 2: Case 1 : Infineon Tricore Case 2 : virtex II Worst case not enough supply pairs, bad distribution & dissymmetry Not ideal Not enough supply for IOs : (core emission is lower than IO one) 11 September 21

Golden Rules for Low Emission Rule 1: Power supply routing strategy Case study 2: 2 FPGA , same power supply, same IO drive, same characte Supply strategy very different ! • More Supply pairs for IOs • Better distribution courtesy of Dr. Howard Johnson, "BGA Crosstalk", www. sigcon. com 12 September 21

Golden Rules for Low Emission Rule 1: Power supply routing strategy Case 1: low emission due to a large number of supply pairs well distributed Case 2: higher emission level (5 times higher) courtesy of Dr. Howard Johnson, "BGA Crosstalk", www. sigcon. com 13 September 21

Golden Rules for Low Emission Rule 2: Add decoupling capacitance Power source Ground referen ce Bulk capacitor (Low frequency) HF capacitor (ceramic) Ferrite Voltage converter / regulator 1 µF – 10 m. F 100 n. F – 1 n. F PCB – Power / ground plane Vdd Vss 1 n. F Transistors, gates, interconnects 14 September 21 Package and IC

Golden Rules for Low Emission Rule 2: Add decoupling capacitance n Equivalent model of a PDN (the most basic model…) PDN ZPDN Vdd ΔVdd Circuit activity Power supply voltage bounce: IIC gnd n Ensuring power integrity relies on the control of a low impedance of the PDN. n A target impedance ZT can be defined as a design objective: ZPDN Zt Target frequency 15 range September 21 Frequency

Golden Rules for Low Emission Rule 2: Add decoupling capacitance Add decoupling capacitor to reduce power supply bounce as close as possible from noise source (current demand) n Principle: Voltage regulator Local charge tank Voltage bounce v(t) Decoupling capacitor IC Vdd Vss Vdd PCB Vss In time domain Large capacitors react rapidly to charge 16 demand. i(t) In frequency domain Large capacitors reduce PDN impedance. September 21

Golden Rules for Low Emission Rule 2: Add decoupling capacitance n Effect of on-board capacitors: X 7 R 50 V ceramic capacitors Parasitic emission (d. BµV) 80 70 60 50 40 30 20 10 -100 10 n. F 0 -10 decoupli 1 ng 100 µF electrolytic capacitor 17 September 21 No decouplin g Customer’s specification 10 – 15 d. B Efficient on one decade 10 100 Frequency (MHz) 1000

Golden Rules for Low Emission Rule 2: Add decoupling capacitance n Example: decoupling of a 16 bit microcontroller (dspic 33 F). n The circuit produces a significant amount of noise over the range 1 – 500 MHz. n We select Zt = 2 Ω. IC Current (1 Ω probe) Z PDN (VNA measurement) Board + IC without decap Antiresonance ZT With 6× 100 n. F decap 18 September 21

Golden Rules for Low Emission Rule 2: Add decoupling capacitance n Example: power integrity of a 16 bit microcontroller (dspic 33 F) with 6× 100 n. F X 7 R decoupling capacitor. n Measurement of power supply voltage in time domain (16 I/O pads switch simultaneously). 19 September 21

Golden Rules for Low Emission Rule 2: Add decoupling capacitance On chip decoupling capacitance versus technology and complexity: Intrinsic on-chip supply capacitance 65 nm 100 n. F 0. 18µm 10 n. F 90 nm 0. 35µm 1. 0 n. F 100 p. F Devices on chip 10 p. F 100 K 1 M 10 M 20 100 M September 21 1 G

Golden Rules for Low Emission Rule 2: Add decoupling capacitance n Effect of on chip capacitance: smooth on-chip voltage fluctuation and reduce conducted emission. n Example: two versions of a CMOS 90 nm digital core, Vdd = 1. 2 V, same mounting board: n n Core 1: No on-chip decoupling capacitance Core 2 : Add 100 p. F MIM decoupling capacitance Vdd bounces measurement 1 ohm conducted measurement 59 m. V 27 m. V 21 September 21 A. Boyer (LAASCNRS)

Golden Rules for Low Emission Rule 2: Add decoupling capacitance n Add limited serial resistor to smooth the voltage drops (too much resistor would increase IR drop and slow down the decap response !) n Effectiveness of decap cells depends on proximity to power supply noise sources. J. Rabaey, Low Power Design Essentials, 2008 22 September 21

Golden Rules for Low Emission Rule 3: Reduce core noise § § § Reduce operating supply voltage Reduce operating frequency Reduce peak current by optimizing IC activity, using distributed clock buffers, turning off unused circuitry, avoiding large loads, creating several operation mode 23 September 21

Golden Rules for Low Emission Rule 3: Reduce core noise § Optimization of bus clock: reduction of buffer’s drive, spread the switching in order to reduce the current peak. J-P. Leca “Microcontrollers Electromagnetic Interferences Modeling and Reduction”, Ph. D report, Univ of Nice, France, 2012 24 September 21

Golden Rules for Low Emission Rule 3: Reduce core noise Add a controlled jitter on clock signal to spread the noise spectrum Clock out Clock in T T+/-Δt Pseudorand om noise P +/-Δf f Spread spectrum frequency modulation specification +/-Δf f 1/T 25 September 21

Golden Rules for Low Emission Rule 3: Reduce core noise - Spread Spectrum Frequency Modulation n Reduction or spreading of clock harmonics by frequency modulation. n Example : sinus clock at Fc = 100 MHz vs modulated sinus clock: Reduction of narrow band RF energy Spread spectrum over B Carrier frequency Fc = 100 MHz Modulation frequency FM = 1 MHz Frequency excursion d. F = +/5 MHz Modulation index md = 5 Carson rule: 26 September 21

Golden Rules for Low Emission Rule 3: Reduce core noise - Spread Spectrum Frequency Modulation n Add a controlled jitter on clock signal to spread the noise spectrum n In practice, a triangular signal is used as modulating signal. Freq. modulation ΔF Clock in Tc Modulant +/- dt t TMod Clock out Tc+/-dt Frequency Modulated Carson ruleclock applies also: d. P Modulat ed clock B Unmodulat ed clock 27 If Fmod < RBW (reso BW of the receiver): September 21

Golden Rules for Low Emission Rule 3: Reduce clock noise – Spread Spectrum Frequency Modulation n Real case study: Effect on emission spectrum produced by the PLL of a 32 microcontroller n Modulation parameters: triangular waveform, FM = 100 KHz, d. F = +/- 0. 64 MHz. n Receiver bandwidth = 10 KHz. Average reduction of 64 MHz harmonics = 10. 6 d. B A. Boyer (LAASCNRS) 28 September 21

Golden Rules for Low Emission Rule 4: Reduce I/O noise • Reduction of the fast rate of I/O current. • Minimize the number of simultaneous switching lines (bus coding) • Reduce di/dt of I/O by controlling slew rate and drive Tr 1 Tr 2 SR & Drive control Emission level 1/Tr 2 1/Tr 1 29 September 21 f

Golden Rules for Low Emission Rule 4: Reduce I/O noise n Example: I/O buffer with Drive and slew rate control options: Full or reduced drive, high and limited slew rate. n Impact of I/O options on timing waveform: Rise time = 2 ns Rise time = 8. 6 ns Full Drive – High slew rate 30 Reduced Drive – High slew rate September 21

Golden Rules for Low Emission Rule 4: Reduce I/O noise n Impact of I/O options on timing waveform and output drive current: What is the more « emissive » option ? The less emissive ? 31 September 21

Golden Rules for Low Emission Rule 4: Reduce I/O noise n Comparison of conducted emission (1 ohm method) 32 September 21

Golden Rules for Low Emission Rule 4: Reduce I/O noise n Comparison of conducted emission (1 ohm method) 33 September 21

Origin of electromagnetic emission Rule 5: Reduce SSN n The switching of output buffer contributes to a large part of conducted and radiated emission. When several I/O switches simultaneously, their contributions tend to add: Simultaneous Switching Noise. n Minimize thenumberof of simultaneous switching lines (bus coding) Effect of the 16 output buffers, two simultaneous switching different switching buffers sequences. 34 September 21

Golden Rules for Low susceptibility Rule 1: Decoupling capacitance is also good for immunity Immunity level (d. Bm) Decoupli ng capacitan ce • DPI aggression of a digital core • Reuse of low emission design rules for susceptibility Substrat e isolation • Efficiency of on-chip decoupling combined with No rules to reduce susceptibility resistive supply path Work done at Eseo France (Ali ALAELDINE) 35 September 21 Frequency

Golden Rules for Low susceptibility Rule 1: Decoupling capacitance is also good for immunity n Example: power integrity of a 16 bit microcontroller (dspic 33 F) with 6× 100 n. F X 7 R decoupling capacitor. n Measurement of conducted immunity (harmonic signal coupled on power supply plane according to DPI standard). At each harmonic frequency, the disturbance power is increased until a circuit failure arises. Max. Power 36 September 21

Golden Rules for Low susceptibility Rule 2: Reduce rectification issues in analog circuits n The following circuits are concerned by the EMI-induced DC offset: opa, voltage regulator, bandgap reference, current mirror, analog output n EMI rectification on a simple analog circuit: Non linear behaviour Once the EMI reaches the non-linear node, the DC offset cannot be filtered 37 DC offset September 21

Golden Rules for Low susceptibility Rule 2: Reduce rectification issues in analog circuits n Example: harmonic injection (100 MHz) on the power supply of a bandgap reference voltage 38 September 21

Golden Rules for Low susceptibility Rule 2: Reduce rectification issues in analog circuits n EMI injection in operational amplifier inputs (weak distortion): Differential current offset: RF disturbances Current source Parasitic capacitors ID 1 Non linear relation ID 2 Offset depends on: § Voltage coupled on diff input and common source X Diff. Pair in saturation regime § Op. Amp bandwidth § Parasitic capacitor CN and Cs 39 § Non linear behavior of MOS devices September 21

Golden Rules for Low susceptibility Rule 2: Reduce rectification issues in analog circuits n Non linearity and parasitic capacitances are the origin of EMI-induced offset in analog circuits (op-amp, output analog buffer, current mirror, voltage reference. . ) n Immunity improvement strategies: è Filter the noise before it reaches a sensitive node (RC filter or increase of input capacitance in differential pair) è Reduce parasitic capacitor è Increase circuit bandwidth è Linearization of input devices è EMI-induced offset cancellation (e. g. crosscoupled differential pair) 40 September 21

Golden Rules for Low susceptibility Rule 3: Isolate Noisy blocks n Example of substrate coupling issue: disturbance of a bandgap voltage reference by the switching of a DC-DC converter embedded within the same circuit Disturbance of bandgap due to substrate coupling A. Boyer (LAASCNRS) DC-DC converter output switching 41 September 21

Golden Rules for Low susceptibility Rule 3: Isolate Noisy blocks Bulk isolation Why ? • To reduce the propagation of switching noise inside the chip • To reduce the disturbance of sensitive blocks by noisy blocks (auto-susceptibility) How ? • by separate voltage supply • by substrate isolation • by increasing separation between sensitive blocks • By reducing crosstalk and parasitic coupling at package level 42 Standard cells Analog Separate supply September 21 Imag perturb DCDC b Noisy blocks Far from noisy blocks

Golden Rules for Low susceptibility Rule 4: Improve noise immunity of IOs • Add Schmitt trigger on digital input buffer • Use differential structures for analog and digital IO to reject common mode noise • Rectification issues due to ESD protection activation during conducted injection (especially with d. V/dt triggering structures) 2 d. B Schmitt trigger 43 September 21