NyquistRate DigitaltoAnalog Converters 0 27 DAC Architectures 1

Nyquist-Rate Digital-to-Analog Converters 0 /27

DAC Architectures 1 /27

DAC Architectures v v Decoder Based Binary-weighted Unit-element (thermometer-coded) Segmented 2 /27

Resistor-String DAC with a Tree-Like Decoder B 1: MSB B 3: LSB 3 /27

Resistor-String DAC with Digital Decoding B 1: MSB B 3: LSB 4 /27

Folded Resistor-String DAC 5 /27

Binary-Weighted Resistor DAC B 1: MSB B 4: LSB 6 /27

Binary-Weighted R-2 R DAC B 1: MSB B 4: LSB 7 /27

Binary-Weighted Current-Mode DAC B 1: MSB B 4: LSB 8 /27

Binary-Weighted Current-Steering DAC bn-1: MSB b 0: LSB 9 /27

Simplified Model 10 /27

Simplified Model 11 /27

Random Mismatch in Current Sources Assuming constant β, we have: Assuming constant Vth, we have: Assuming Vth and β are independent and have Gaussian pdf, we have: Variances of Vth and β depend on W×L and technology as follows: 12 /27

Example 13 /27

Con’td 14 /27

Binary-Weighted Charge-Redistribution DAC B 0: LSB Bn-1: MSB 15 /27

Binary-Weighted Charge-Redistribution DAC B 0: LSB Bn-1: MSB 16 /27

Binary-Weighted Charge-Redistribution DAC B 0: LSB Bn-1: MSB 17 /27

Binary-Weighted Hybrid Capacitive-Resistive DAC B 0: LSB Bn-1: MSB Overall Resolution: n+3 18 /27

Glitch Problem of the Binary-Weighted DAC Due to timing error , we may have: 19 /27

Glitch Problem (cont’d) 20 /27

Unit Element (Thermometer code) DAC 21 /27

Unit Element DAC (cont’d) 22 /27

Segmented DAC v v v MSB DAC: M-bit Unit Element DAC LSB DAC: L-bit Binary Weighted DAC Resolution: N = M + L 2 M+L switching elements Small glitches 23 /27

Segmented DAC 24 /27

Segmented DAC Current Steering DAC 25 /27

Current Cell 26 /27

Commercial Example (AD 9754) 27 /27

Segmented DAC 28 /27