Metrics for Reconfigurable Architectures Characterization Remanence and Scalability
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability Pascal BENOIT G. Sassatelli – L. Torres – D. Demigny M. Robert – G. Cambon Name. Surname@lirmm. fr
Outline q Context q Remanence q Operative Density q Case Study: the Systolic Ring q Conclusion and perspectives
Context q So. C and Customizable Platform Based-Design DSP Specifications Processing power Area Power consumption etc. Reconfigurable Hardware (Fine Grain) ASIC 1 ASIC 2 Reconfigurable Hardware (Coarse Grain) We need metrics to compare !
Context q Architecture characterization • • q Processing power Power consumption Flexibility Parallelism potential Dynamism Silicon area Scalability … Metrics Generalisation to Architectural model characterisation and metrics depend on architectural parameters Dehon criterion • Remanence • Operative density • « Comparing architectures with a minimum of criteria »
Remanence q Definition Fc Fe q NPE: # of processing elements (PE) Nc: # of PE configurable per cycle Fe: operating frequency Fc configuration frequency Characterizes the Dynamism ü # of cycles to (re)configure the whole architecture ü Amount of data to compute between 2 configurations
Remanence q Comparisons Name Type NPE Nc F (MHz) R ARDOISE Fine Grain RA 2304 0. 14 33 16457 Morpho. Sys Coarse Grain RA 128 16 100 8 Systolic Ring Coarse Grain RA 24 4 200 6 DART Coarse Grain RA 24 4 130 6 8 8 300 1 TMS 320 C 62 DSP VLIW ü Only 1 cycle to (re)configure the DSP ü Few cycles to (re)configure coarse grain RA ( 8) ü Many cycles to (re)configure fine grain RA
Operative Density q Definition NPE: # of PE A: Core Area (relative unit ²) Area can be expressed as a function of NPE (architectural model) q Characterizes ü Fixed NPE • ü # of operators per relative area unit Variable NPE • OD as a function of NPE A(NPE) = NPE*APE+Ainterconnect(NPE)+Amemory(NPE) Asequencer(NPE) • OD(NPE) = k A(NPE) =k. NPE the architectural model is scalable
Operative Density q Comparisons Name Type NPE Area(Ml²) ARDOISE Fine Grain RA 26 12300 0. 2 Systolic Ring (S=1, C=6, N=2) Coarse Grain RA 24 500 4. 8 DART Coarse Grain RA 24 300 8. 0 Systolic Ring (S=1, C=16, N=4) Coarse Grain RA 128 7600 1. 7 Morpho. Sys Coarse Grain RA 128 5500 2. 3 8 12300 0. 1 TMS 320 C 62 ü ü DSP VLIW DSP: sequencer area ARDOISE : fine granularity Coarse granularity Reconfigurable architectures Scalabilty of interconnect resources ? • Generalization to architectural models • OD (NPE)
-Architectural Model Characterization A Case Study: The Systolic Ring
Architectural model Characterization q The Systolic Ring Architectural model ü Based on a coarse-grained configurable PE
Architectural model Characterization The Systolic Ring Architectural model Dnode h it it c Dnode Sw Sw ch Dnode h ü Based on a coarse-grained configurable PE Circular datapaths Dnode it c ü Sw q Dnode Sw it ch Dnode
Architectural model Characterization The Systolic Ring Architectural model ü ü Dnode Sw it c h layer 4 C: # of layers • N: # of Dnodes per layer Dnode Dnode # of layers : 4 (C = 4) # of Dnode per layer : 2 (N = 2) Sw it c h • ch Based on a coarse-grained configurable PE Circular datapaths 3 parameters it ü layer 1 Sw q Dnode layer 3 Dnode Sw layer 2 it ch
Architectural model Characterization q The Systolic Ring Architectural model ü ü ü Based on a coarse-grained configurable PE Circular datapaths 3 parameters layer 1 layer 2 layer 8 layer 3 C: # of layers • N: # of Dnodes per layer • layer 7 layer 4 # of layers : 8 (C = 8) # of Dnode per layer : 2 (N = 2) layer 6 layer 5
Architectural model Characterization q The Systolic Ring Architectural model ü ü ü Based on a coarse-grained configurable PE Circular datapaths 3 parameters layer 1 layer 2 layer 8 layer 3 C: # of layers • N: # of Dnodes per layer • S: # of Rings • layer 7 layer 4 # of layers : 8 (C = 8) # of Dnode per layer : 2 (N = 2) 1 Systolic Ring (S = 1) layer 6 layer 5
Architectural model Characterization q The Systolic Ring Architectural model ü ü ü Based on a coarse-grained configurable PE Circular datapaths 3 parameters C: # of layers • N: # of Dnodes per layer • S: # of Rings • # of layers : 4 (C = 4) # of Dnode per layer : 2 (N = 2) 4 Systolic Ring (S = 4)
Architectural model Characterization q The Systolic Ring Architectural model ü ü ü Based on a coarse-grained configurable PE Circular datapaths 3 parameters C: # of layers • N: # of Dnodes per layer • S: # of Rings • ü Control Units • Local Dnodes units Dnode Sequencer
Architectural model Characterization q The Systolic Ring Architectural model ü ü ü Based on a coarse-grained configurable PE Circular datapaths 3 parameters Local Ring Sequencer C: # of layers • N: # of Dnodes per layer • S: # of Rings • ü Control Units Local Dnode unit • Local Ring unit •
Architectural model Characterization q The Systolic Ring Architectural model ü ü ü Based on a coarse-grained configurable PE Circular datapaths 3 parameters Global Sequencer Local Ring Sequencer C: # of layers • N: # of Dnodes per layer • S: # of Rings • ü Control Units Local Dnode unit • Local Ring unit • Global unit •
Architectural model Characterization q Remanence ü Only one Systolic Ring S=1 ü NPE = # of Dnodes = N*C*S = N*C ü Remanence formalisation • k= C/N
Architectural model Characterization q A(NPE) formalisation for OD(NPE) ü ü 0. 18µ CMOS technology • C = 4, N = 2, S = 1 • A(8) = 3. 3 mm ² • A(8) = 407 M ² Area formalisation: • A ( NPE ) = f ( N, C, S ) depends on C / N ratio and S • NPE = N. C. S Systolic Ring layout (C=4, N=2, S=1) Area formalisation calibrated on these results
Architectural model Characterization q q OD(NPE) for 1 Systolic Ring (S=1) ü k = C/N = [ 0. 25 ; 4 ] ü decreasing OD(NPE) for several Systolic Ring ü k = C/N = 4 ü multi-ring instanciations increase scalability
Architectural model Characterization q Customisation and design technique • between 60 and 80 processing elements
Architectural model Characterization q Customisation and design technique • between 60 and 80 processing elements
Architectural model Characterization q Customisation and design technique Design Space
Architectural model Characterization Best OD and remanence Worst interconnect resources and processing power Design Space
Architectural model Characterization Worst OD and remanence Best interconnect resources and processing power Design Space
Architectural model Characterization R and OD can be integrated in CAD tools to observe architectural parameters effects and choose best tradeoffs in the design space
Conclusion and perspectives IP 1 R 1 OD 1 R 2 Specifications Processing power Area Power consumption etc. IP 2 OD 2 R 3 IP 3 OD 3 IP n Rn ODn
Conclusion and perspectives IP 1 R 1 OD 1 R 2 Specifications Processing power Area Power consumption etc. IP 2 OD 2 R 3 IP n OD 3 Rn Architectural models Comparisons ODn
Conclusion and perspectives IP 1 R 1 OD 1 R 2 Specifications Processing power Area Power consumption etc. IP 2 OD 2 R 3 IP n OD 3 Rn Architectural model Customisation ODn
Thank You
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