Metastability When Good FlipFlop Goes Bad Causes and

Metastability - When Good Flip-Flop Goes Bad: Causes and Cure Instructor: Dr. Rehan Ahmed [rehan. ahmed@seecs. edu. pk] Slide 1 1

Learning Objectives 1. Understand what metastability is, and how it can cause failure 2. Understand why metastability happens 3. Be able to design a circuit to reduce the probability that metastability causes system failure 4. To be able to calculate the mean time between failure due to metastability 2

What happens if we violate a flip-flop’s setup and/or hold time requirements? 3

Violating Flip-Flop Setup/Hold Times Setup/Hold Requirement not met t setup t hold D D CLK DFF Q CLK Q ? ? ? Possible Outcomes: Q may… • get the wrong value (0 or 1) • get the correct value • become metastable - get a value between 0 and 1 • Remember, in reality, we are working with voltages which can take on a continuous range of values 4

Metastability t D setup t hold D Q To rest of your system TIMING VIOLATION CLK Q METASTABILITY logic 1 logic 0 METASTABLE VALUE PROPOGATED TO OTHER PARTS OF SYSTEM MAY CAUSE SYSTEM-WIDE FAILURE 5

Real Metastable Example Picture taken from W. J. Dally, Lecture notes for EE 108 A, Lecture 13: Metastability and Synchronization Failure (ow When Good Flip-Flops go Bad) 11/9/2005. 6

Real Metastable Example Picture taken from W. J. Dally, Lecture notes for EE 108 A, Lecture 13: Metastability and Synchronization Failure (ow When Good Flip-Flops go Bad) 11/9/2005. 7

Why System Failure? DESTINATION FFs BECOME METASTABLE BUT RESOLVES TO 0 RESOLVES TO 1 METASTABLE VALUE PROPGATED INCONSISTENT! If metastable value is propagated, FFs at next stage will become metastable and may… • further propagate metastable value • or resolve inconsistently • different destinations FFs see different values for the same signal 8

Why does Metastability happen? 9

Mechanical Analogy BALL Hill Imagine dropping a ball on a hill • perfectly smooth and symmetrical hill • no forces except gravity Depending on where you drop the ball, it will settle in one of two states • either on the left side or the right side 10

Mechanical Analogy BALL Hill The closer you drop the ball near either side, the faster it settles • Shorter distance • Steeper slope 11

Mechanical Analogy Two Stable States BALL Hill BALL Once ball reaches either state, it will stay there forever 12

Mechanical Analogy There is a THIRD “metastable” state! BALL Hill Imagine the ball is dropped perfectly in the middle The slope at the exact middle is flat There are no other forces besides gravity In theory, ball will stay there forever 13

Mechanical Analogy Wind BALL Hill In practice, ball will eventually settle to a stable state • Gust of wind • Non-perfect hill • Not perfectly symmetrical • Slope not perfectly flat in the middle 14

Mechanical Analogy ? BALL ? Hill Into which state will it settle? How long before it settles? Not predictable! 15

OK, Got it! But how does this apply to flip-flops? 16

A Theoretical Storage Element A B Two Stable States • A=0, B=1 • A=1, B=0 This element isn’t very practical (no way to change state) But ALL state-holding digital circuits* are based off of using positive-feedback loops 17

Preview – Possible Topology for a D-Latch CLK Q D CLK When CLK is 1, /Q follows D (but inverted) When CLK is 0, D is disconnected, feedback loop is connected to reinforce “stored” value, /Q does not change with D 18

Inverter Voltage Transfer Curve (VTC) Vout Vin Vout 1. 8 V IDEAL Say that in our technology: Logic 1 is 1. 8 V Logic 0 is 0 V 0. 9 V IDEAL Behaviour: Vout 1. 8 V, Vin 0. 9 V 0 V, Vin 0. 9 V Vin 0 V 0. 9 V 1. 8 V Slide 19 19

Inverter Voltage Transfer Curve (VTC) Vout Vin Vout 1. 8 V REALISTIC Say that in our technology: Logic 1 is 1. 8 V Logic 0 is 0 V 0. 9 V REALISTIC Behaviour Vout f Vin 0 V 0. 9 V 1. 8 V Slide 20 20

Storage Element – Scenario 1 Say we externally drive A to 0 V 0 V 1. 8 V 1. B gets driven to 1. 8 V by the B A top inverter 2. A then gets driven to 0 V by the bottom inverter (reinforced) 0 V 1. 8 V Vout 3. which then causes B to be driven to 1. 8 V (reinforced) 1. 8 V 4. … 1. 35 V Positive feedback INSTANTLY reinforces Internal value. 0. 9 V 0. 45 V Vin 0 V 0. 45 V 0. 9 V 1. 35 V 1. 8 V 21

Storage Element – Scenario 2 Say we externally drive A to 1. 8 V 0 V A 1. B gets driven to 0 V by the B 1. 8 V 0 V top inverter 2. A then gets driven to to 1. 8 V by the bottom inverter (reinforced) Vout 3. which then causes B to be 1. 8 V driven to 0 V (reinforced) 1. 35 V • 4. … 0. 9 V 0. 45 V Vin 0 V 0. 45 V 0. 9 V 1. 35 V 1. 8 V Positive feedback INSTANTLY reinforces Internal value. 22

Storage Element – Scenario 3 Say we externally drive A to 0. 9 V B A 0. 9 V 1. B gets driven to 0. 9 V by the top inverter 2. A then gets driven to to 0. 9 V by the bottom inverter Vout 1. 8 V 3. which then causes B to be 1. 35 V driven to 0. 9 V • 4. … 0. 45 V Vin 0 V 0. 45 V 0. 9 V 1. 35 V 1. 8 V STUCK IN METASTABLE STATE! 23

Storage Element – Metastable State 0. 9 V B A 0. 9 V In reality, there are sources of noise: • Thermal, crosstalk, quantum transistor effects • Noise is like the “gust of wind” from mechanical example NOISE will push the circuit out of metastability • But we won’t know how long this will take • Nor will we know which of the two stable states it will assume 24

Back to Set-up and Hold times. . . 25

Violating Setup or Hold Time Requirements t D setup t hold Setup time not met. Timing “just right” and leaves D’ at 0. 9 V CLK Q METASTABILITY May resolve to 1 May resolve to 0 tclk-to-q t resolution Takes extra time for Q to settle Resolution time is UNBOUNDED 26

If tresolution is GREATER than the amount of path slack, then system failure! 27

Bottom Line: Don’t change flip-flop input too close to clockedge 28

Dealing with Metastability … 29

Dealing With Metastability Possible Options? • Eliminate all possibility of metastability • Reduce probability that metastability would cause failure 30

Eliminating Metastability? DFF Combinational Logic tcrit 0 DFF Combinational Logic tcrit 1 DFF … The whole point of synchronization: Within our circuit, make sure both setup and hold requirements are always met for all paths We can eliminate metastability inside of our circuit But we often need to interface with asynchronous signals 31

Asynchronous Signals Asynchronous just mean that it doesn’t adhere to the clock signal For Example: Real World Signals • Real world signals, like buttons, don’t change aligned to your clock • Non-zero chance of input changing too close to clock edge Real world (Sensor, Button, etc. ) DFF To rest of your system 32

Asynchronous Signals Another Example: Systems With Multiple Clocks • Many systems have more than one clock • Flip-flops still only listen to one clock • Logic/FFs on the same clock belong to the same clock-domain Signals sometime need to cross clock-domain boundaries If the clocks are unsynchronized (not multiples of each other), then the signal crossing the clock-domain appears asynchronous Clock Domain Boundary A DFF CLK 1 DFF CLK 2 Signal A appears asynchronous to DFF 2 33

Reduce Probability that Metastable State Causes System Failure Async Input S CLK Synchronizer Circuit • Two flip-flops instead of one • If S goes metastable, it has an entire clock-cycle to resolve itself This is a VERY common technique – add synchronizers to all async interfaces 34

Mean-time Between Failure Metric to estimate the average time between two failurecausing instances of metastability on a given signal transfer e tslack /C 0 MTBF C 1 f. CLK f DATA • f. CLK – Clock frequency • f. DATA – Toggling frequency of the FF input • tslack – Amount of slack available on the path for metastability resolution • Co , C 1 – Constants dependent on operating conditions and process tech 35

Mean-time Between Failure Metric to estimate the average time between two failurecausing instances of metastability on a given signal transfer e tslack /C 0 MTBF tslack C 1 f. CLK f DATA Higher MTBF means more robust design • maybe hundreds or thousands of years Required MTBF depends on application • Life-critical medical equipment would need higher MTBF than consumer video game system 36

MTBF Example Calculation - Synchronizer S Async Input f. CLK = 100 MHz f. DATA = 1 MHz tslack = 2. 3 ns Co = 0. 31 ns C 1=9. 6 *10 -18 s CLK MTBF e tslack /C 0 C 1 f. CLK f. DATA 20. 1 days Quartus calculates all this for you! 37

THANK YOU

S l i d e D Flip-Flop – Master-Slave Topology S e t 1 2 , P a g e 3 9 CLK D CLK S' S D’ master CLK Q slave Built using two D-Latches Slide 39 39

S l i d e D Flip-Flop – Master-Slave Topology S e t 1 2 , P a g e 4 0 CLK D CLK S' S D’ master CLK Q slave Built using two D-Latches • When CLK = 0 • master is in pass-through mode D S • slave is disconnected from master • slave in feedback mode and S ’ Q SETUP Time is essentially time to charge up node S 40

S l i d e D Flip-Flop – Master-Slave Topology S e t 1 2 , P a g e 4 1 CLK D CLK S' S D’ master CLK Q slave Built using two D-Latches • When CLK = 1 • master is in feedback mode • master value passed to slave S passed to S’ • slave in pass-through mode S Q HOLD Time is essentially time for D D’ switch to turn off 41

S l i d e Violating Setup or Hold Time Requirements S e t 1 2 , P a g e 4 2 CLK D 0. 9 V master CLK 0. 9 V S' S D’ CLK = 1 Q 0. 9 V CLK 0. 9 V slave 0. 9 V Risks putting 0. 9 V onto S or D’ • We know that the master feedback look could be stuck in metastable state for unknown amount of time • Will also put slave into metastable state • Q would then be metastable Noise will eventually knock out of metastable state 42

S l i d e Violating Setup or Hold Time Requirements S e t 1 2 , P a g e 4 3 CLK D S' S D’ CLK = 0 Q 0. 9 V CLK master 0. 9 V slave CLK 0. 9 V After falling edge • Slave feedback gets stuck in metstable state • Q still metastable Noise will eventually knock out of metastable state 43

Storage Element – Scenario 4 Say we externally drive A to 1 V 1. B gets driven to 0. 75 V by the top inverter 1. 8 V 2. A then gets driven to to 0 V 1. 5 V by the bottom B A 1. 8 V inverter 3. which then causes B 0 V to be driven to 0. 2 V Vout • 4. … 1. 8 V 1. 35 V Positive feedback TAKING LONGER now to settle internal value. 0. 9 V 0. 45 V Vin 0 V 0. 45 V 0. 9 V 1. 35 V 1. 8 V 44

Storage Element – Scenario 3 Say we externally drive A to 1. 35 V 1. 8 V 0 V 1. B gets driven to 0. 2 V by the B A top inverter 2. A then gets driven to to 1. 75 V by the bottom inverter 1. 8 V 0 V 3. which then causes B to be Vout driven to 0. 01 V 1. 8 V 4. … 1. 35 V Positive feedback VERY QUICKLY settles Internal value. 0. 9 V 0. 45 V Vin 0 V 0. 45 V 0. 9 V 1. 35 V 1. 8 V 45