Introduction to parallel processing Chapter 1 from Culler

Introduction to parallel processing Chapter 1 from Culler & Singh Winter 2007 0

Introduction n What is Parallel Architecture? n Why Parallel Architecture? n Evolution and Convergence of Parallel Architectures n Fundamental Design Issues Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 1

What is Parallel Architecture? n A parallel computer is a collection of processing elements that cooperate to solve large problems fast n Some broad issues: n Resource Allocation: n n Data access, Communication and Synchronization n n how do the elements cooperate and communicate? how are data transmitted between processors? what are the abstractions and primitives for cooperation? Performance and Scalability n n Winter 2007 how large a collection? how powerful are the elements? how much memory? how does it all translate into performance? how does it scale? ENGR 9861 R. Venkatesan High-Performance Computer Architecture 2

Why Study Parallel Architecture? n Role of a computer architect: n To design and engineer the various levels of a computer system to maximize performance and programmability within limits of technology and cost. n Parallelism: n n Winter 2007 Provides alternative to faster clock for performance Applies at all levels of system design Is a fascinating perspective from which to view architecture Is increasingly central in information processing ENGR 9861 R. Venkatesan High-Performance Computer Architecture 3

Why Study it Today? n History: diverse and innovative organizational structures, often tied to novel programming models n Rapidly maturing under strong technological constraints n The “killer micro” is ubiquitous n Laptops and supercomputers are fundamentally similar! n Technological trends cause diverse approaches to converge n Technological trends make parallel computing inevitable n In the mainstream n Need to understand fundamental principles and design tradeoffs, not just taxonomies n Winter 2007 Naming, Ordering, Replication, Communication performance ENGR 9861 R. Venkatesan High-Performance Computer Architecture 4

Application Trends n Demand for cycles fuels advances in hardware, and vice-versa n Cycle drives exponential increase in microprocessor performance n Drives parallel architecture harder: most demanding applications n Range of performance demands n Need range of system performance with progressively increasing cost n Platform pyramid n Goal of applications in using parallel machines: Speedup (p processors) = Performance (p processors) Performance (1 processor) n For a fixed problem size (input data set), performance = 1/time Time (1 processor) Speedup fixed problem (p processors) = Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture Time (p processors) 5

Scientific Computing Demand Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 6

Engineering Computing Demand n Large parallel machines a mainstay in many industries, for example, n n n n Winter 2007 Petroleum (reservoir analysis) Automotive (crash simulation, drag analysis, combustion efficiency), Aeronautics (airflow analysis, engine efficiency, structural mechanics, electromagnetism), Computer-aided design Pharmaceuticals (molecular modeling) Visualization n in all of the above n entertainment (films like Shrek 2, The Incredibles) n architecture (walk-throughs and rendering) Financial modeling (yield and derivative analysis). ENGR 9861 R. Venkatesan High-Performance Computer Architecture 7

Applications: Speech and Image Processing • Also CAD, Databases, . . . • 100 processors gets you 10 years! Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 8

Learning Curve for Parallel Applications n AMBER molecular dynamics simulation program n Starting point was vector code for Cray-1 n 145 MFLOP on Cray 90, 406 for final version on 128 -processor Paragon, 891 on 128 -processor Cray T 3 D Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 9

Commercial Computing n Also relies on parallelism for high end n n Scale not so large, but use much more wide-spread Computational power determines scale of business that can be handled n Databases, online-transaction processing, decision support, data mining, data warehousing. . . n TPC benchmarks (TPC-C order entry, TPC-D decision support) n n n Winter 2007 Explicit scaling criteria provided Size of enterprise scales with size of system Problem size no longer fixed as p increases, so throughput is used as a performance measure (transactions per minute or tpm) ENGR 9861 R. Venkatesan High-Performance Computer Architecture 10

Summary of Application Trends n Transition to parallel computing has occurred for scientific and engineering computing n In rapid progress in commercial computing n n Database and transactions as well as financial Usually smaller-scale, but large-scale systems also used n Desktop also uses multithreaded programs, which are a lot like parallel programs n Demand for improving throughput on sequential workloads n Greatest use of small-scale multiprocessors n Solid application demand exists and will increase Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 11

Technology Trends The natural building block for multiprocessors is now also about the fastest! Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 12

General Technology Trends Microprocessor performance increases 50% - 100% per year Transistor count doubles every 3 years DRAM size quadruples every 3 years Huge investment per generation is carried by huge commodity market Not that single-processor performance is plateauing, but that parallelism is a natural way to improve it. n n n 180 160 140 DEC alpha 120 100 80 60 40 20 MIPS Sun 4 M/120 260 0 1987 Winter 2007 1988 MIPS M 2000 1989 IBM RS 6000 540 1990 Integer FP HP 9000 750 1991 1992 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 13

Technology: A Closer Look n Basic advance is decreasing feature size ( ) n Circuits become either faster or lower in power n Die size is growing too n Clock rate improves roughly proportional to improvement in n Number of transistors improves like (or faster) n Performance > 100 x per decade; clock rate 10 x, rest transistor count n How to use more transistors? n Parallelism in processing n n Proc $ Locality in data access n n n multiple operations per cycle reduces CPI avoids latency and reduces CPI also improves processor utilization Interconnect Both need resources, so tradeoff n Fundamental issue is resource distribution, as in uniprocessors Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 14

Clock Frequency Growth Rate • 30% per year Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 15

Transistor Count Growth Rate • 100 million transistors on chip by early 2000’s A. D. • Transistor count grows much faster than clock rate - 40% per year, order of magnitude more contribution in 2 decades Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 16

Storage Performance n Divergence between memory capacity and speed more pronounced n n Capacity increased by 1000 x from 1980 -2005, speed only 5 x 4 Gigabit DRAM now, but gap with processor speed much greater n Larger memories are slower, while processors get faster n Need to transfer more data in parallel n Need deeper cache hierarchies n How to organize caches? n Parallelism increases effective size of each level of hierarchy, without increasing access time n Parallelism and locality within memory systems too n n New designs fetch many bits within memory chip; follow with fast pipelined transfer across narrower interface Buffer caches most recently accessed data n Disks too: Parallel disks plus caching Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 17

Architectural Trends n Architecture translates technology’s gifts to performance and capability n Resolves the tradeoff between parallelism and locality n n Current microprocessor: 1/3 compute, 1/3 cache, 1/3 off-chip connect Tradeoffs may change with scale and technology advances n Understanding microprocessor architectural trends n Helps build intuition about design issues or parallel machines n Shows fundamental role of parallelism even in “sequential” computers n Four generations of architectural history: tube, transistor, IC, VLSI n Here focus only on VLSI generation n Greatest delineation in VLSI has been in type of parallelism exploited Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 18

Architectural Trends in VLSI n Greatest trend in VLSI generation is increase in parallelism n Up to 1985: bit level parallelism: 4 -bit -> 8 bit -> 16 -bit n slows after 32 bit n adoption of 64 -bit now under way, 128 -bit far (not performance issue) n great inflection point when 32 -bit micro and cache fit on a chip n Mid 80 s to mid 90 s: instruction level parallelism n pipelining and simple instruction sets, + compiler advances (RISC) n on-chip caches and functional units => superscalar execution n greater sophistication: out of order execution, speculation, prediction n to deal with control transfer and latency problems n 2000 s: Thread-level parallelism Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 19

ILP Ideal Potential • Infinite resources and fetch bandwidth, perfect branch prediction and renaming – real caches and non-zero miss latencies Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 20

Raw Uniprocessor Performance: LINPACK 10, 000 n CRAY s CRAY l Micro u Micro 1, 000 x 1000 matrix 100 matrix n LINPACK (MFLOPS) 1, 000 n T 94 s l C 90 s n n s 100 s l n Ymp Xmp/416 s DEC 8200 l u u l l u IBM Power 2/990 MIPS R 4400 Xmp/14 se l l DEC Alpha u u. HP 9000/735 u. DEC Alpha AXP u HP 9000/750 sn CRAY 1 s u. IBM RS 6000/540 10 l l MIPS M/2000 u MIPS M/120 u 1 1975 Winter 2007 Sun 4/260 u l 1980 1985 1990 1995 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 2000 21

Summary: Why Parallel Architecture? n Increasingly attractive n Economics, technology, architecture, application demand n Increasingly central and mainstream n Parallelism exploited at many levels n Instruction-level parallelism n Multiprocessor servers n Large-scale multiprocessors (“MPPs”) n Focus of this class: multiprocessor level of parallelism n Same story from memory system perspective n Increase bandwidth, reduce average latency with many local memories n Wide range of parallel architectures make sense n Different cost, performance and scalability Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 22

History of parallel architectures n Historically, parallel architectures tied to programming models n n Divergent architectures, with no predictable pattern of growth. Uncertainty of direction paralyzed parallel software development! Application Software Systolic Arrays Dataflow Winter 2007 System Software Architecture SIMD Message Passing Shared Memory ENGR 9861 R. Venkatesan High-Performance Computer Architecture 23

Today’s architectural viewpoint n Architectural enhancements to support communication and cooperation n n OLD: Instruction Set Architecture NEW: Communication Architecture n Defines n Critical abstractions, boundaries, and primitives (interfaces) n Organizational structures that implement interfaces (h/w or s/w) n Compilers, libraries and OS are important bridges today Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 24

Modern Layered Framework CAD Database Multiprogramming Shared address Scientific modeling Message passing Data parallel Compilation or library Operating systems support Communication hardware Parallel applications Programming models Communication abstraction User/system boundary Hardware/software boundary Physical communication medium Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 25

Programming Model n What programmer uses in coding applications n Specifies communication and synchronization n Examples: n Multiprogramming: no communication or synch. at program level n Shared address space: like bulletin board n Message passing: like letters or phone calls, explicit point to point n Data parallel: more regimented, global actions on data n Winter 2007 Implemented with shared address space or message passing ENGR 9861 R. Venkatesan High-Performance Computer Architecture 26

Communication Abstraction n User level communication primitives provided n Realizes the programming model n Mapping exists between language primitives of programming model and these primitives n Supported directly by HW, or via OS, or via user SW n Lot of debate about what to support in SW and gap between layers n Today: n n n HW/SW interface tends to be flat, i. e. complexity roughly uniform Compilers and software play important roles as bridges today Technology trends exert strong influence n Result is convergence in organizational structure n Relatively simple, general purpose communication primitives Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 27

Communication Architecture n Comm. Arch. = User/System Interface + Implementation n User/System Interface: n Comm. primitives exposed to user-level by HW and system-level SW n Implementation: n Organizational structures that implement the primitives: HW or OS n How optimized are they? How integrated into processing node? n Structure of network n Goals: n Performance n Broad applicability n Programmability n Scalability n Low Cost Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 28

Evolution of Architectural Models n Historically machines tailored to programming models n Prog. model, comm. abstraction, and machine organization lumped together as the “architecture” n Evolution helps understand convergence n Identify core concepts n Shared Address Space n Message Passing n Data Parallel n Others: n Dataflow n Systolic Arrays n Examine programming model, motivation, intended applications, and contributions to convergence Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 29

Shared Address Space Architectures n Any processor can directly reference any memory location n Communication occurs implicitly as result of loads and stores n Convenient: n Location transparency n Similar programming model to time-sharing on uniprocessors n n Except processes run on different processors Good throughput on multiprogrammed workloads n Naturally provided on wide range of platforms n History dates at least to precursors of mainframes in early 60 s n Wide range of scale: few to hundreds of processors n Popularly known as shared memory machines or model n Ambiguous: memory may be physically distributed among processors Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 30

Shared Address Space Model n Process: virtual address space plus one or more threads of control n Portions of address spaces of processes are shared Virtual address spaces for a collection of processes communicating via shared addresses Load P 1 Machine physical address space Pn pr i v at e Pn Common physical addresses P 2 P 0 St or e Shared portion of address space Private portion of address space P 2 pr i vat e P 1 pr i vat e P 0 pr i vat e n Writes to shared address visible to other threads (in other processes too) n n Winter 2007 Natural extension of uniprocessors model: conventional memory operations for comm. ; special atomic operations for synchronization OS uses shared memory to coordinate processes ENGR 9861 R. Venkatesan High-Performance Computer Architecture 31

Communication Hardware in SAS arch. n Also natural extension of uniprocessor n Already have processor, one or more memory modules and I/O controllers connected by hardware interconnect of some sort n Memory capacity increased by adding modules, I/O by controllers n n Winter 2007 Add processors for processing! For higher-throughput multiprogramming, or parallel programs ENGR 9861 R. Venkatesan High-Performance Computer Architecture 32

History of SAS architectures n Mainframe” approach n n n Motivated by multiprogramming Extends crossbar used for mem bw and I/O Originally processor cost limited to small n n n later, cost of crossbar Bandwidth scales with p High incremental cost; use multistage instead n “Minicomputer” approach n n n Almost all microprocessor systems have bus Motivated by multiprogramming, TP Used heavily for parallel computing Called symmetric multiprocessor (SMP) Latency larger than for uniprocessor Bus is bandwidth bottleneck n n Winter 2007 caching is key: coherence problem Low incremental cost ENGR 9861 R. Venkatesan High-Performance Computer Architecture 33

Example of SAS: Intel Pentium Pro Quad All coherence and multiprocessing glue in processor module n Highly integrated, targeted at high volume n Low latency and bandwidth n Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 34

Example of SAS: SUN Enterprise n 16 cards of either type: processors + memory, or I/O n All memory accessed over bus, so symmetric n Higher bandwidth, higher latency ENGR 9861 R. Venkatesan Winterbus 2007 High-Performance Computer Architecture 35

Scaling Up SAS Architecture “Dance hall” n n Problem is interconnect: cost (crossbar) or bandwidth (bus) Dance-hall: bandwidth still scalable, but lower cost than crossbar n n latencies to memory uniform, but uniformly large Distributed memory or non-uniform memory access (NUMA) n n Distributed memory Construct shared address space out of simple message transactions across a general-purpose network (e. g. read-request, read-response) Caching shared (particularly nonlocal) data? Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 36

Example scaled-up SAS arch. : Cray T 3 E n Scale up to 1024 processors, 480 MB/s links Memory controller generates comm. request for nonlocal references n No hardware mechanism for coherence (SGI Origin etc. provide this n Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 37

Message Passing Architectures n Complete computer as building block, including I/O n Communication via explicit I/O operations n Programming model: directly access only private address space (local memory), comm. via explicit messages (send/receive) n High-level block diagram similar to distributed-memory SAS n But comm. integrated at IO level, needn’t be into memory system n Like networks of workstations (clusters), but tighter integration n Easier to build than scalable SAS n Programming model more removed from basic hardware operations n Winter 2007 Library or OS intervention ENGR 9861 R. Venkatesan High-Performance Computer Architecture 38

Message-Passing Abstraction Match Receive. Y, P, t Address. Y Send. X, Q, t Address. X n n n Local process address space Process P Process Q Send specifies buffer to be transmitted and receiving process Recv specifies sending process and application storage to receive into Memory to memory copy, but need to name processes Optional tag on send and matching rule on receive User process names local data and entities in process/tag space too In simplest form, the send/recv match achieves pairwise synch event n n Local process address space Other variants too Many overheads: copying, buffer management, protection Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 39

Evolution of Message-Passing Machines n Early machines: FIFO on each link n Hw close to prog. Model; synchronous ops n Replaced by DMA, enabling non-blocking ops n Buffered by system at destination until recv n Diminishing role of topology n Store&forward routing: topology important n Introduction of pipelined routing made it less so n Cost is in node-network interface n Simplifies programming Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 40

Example of MP arch. : IBM SP-2 n n Made out of essentially complete RS 6000 workstations Network interface integrated in I/O bus (bw limited by I/O bus) Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 41

Example Intel Paragon Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 42

Toward Architectural Convergence n Evolution and role of software have blurred boundary n Send/recv supported on SAS machines via buffers n Can construct global address space on MP using hashing n Page-based (or finer-grained) shared virtual memory n Hardware organization converging too n Tighter NI integration even for MP (low-latency, high-bandwidth) n At lower level, even hardware SAS passes hardware messages n Even clusters of workstations/SMPs are parallel systems n Emergence of fast system area networks (SAN) n Programming models distinct, but organizations converging n Nodes connected by general network and communication assists n Implementations also converging, at least in high-end machines Winter 2007 ENGR 9861 R. Venkatesan High-Performance Computer Architecture 43