EET 1131 Unit 11 Counter Circuits Read Kleitz

EET 1131 Unit 11 Counter Circuits ¡ ¡ ¡ Read Kleitz, Chapter 12, skipping Sections 12 -10 and 12 -11. (Note that we are skipping Chapter 11. ) Homework #11 and Lab #11 due next week. Quiz next week.

Counting is a very common operation in digital systems. Some examples on a macro-scale: ¡ l l l Counting the number of times a microwave-oven button was pressed. Counting the number of objects that pass on a conveyor belt. Counting the number of cars entering or leaving a parking lot. Some examples on a micro-scale: ¡ l l Counting the number of bytes that enter from a modem. Counting the number of clock cycles since an internal control signal went HIGH.

Counting in Binary As you know, the binary count sequence follows a familiar pattern of 0’s and 1’s as described in Section 2 -2 of the text. 000 001 010 011 100 The next bit changes on 101 every fourth number. 110 111 LSB changes on every number. The next bit changes on every second number. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Counting in Binary A counter can form the same pattern of 0’s and 1’s with logic levels. The first stage in the counter represents the least significant bit – notice that these waveforms follow the same pattern as counting in binary. LSB MSB © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Two Basic Counter Designs ¡ ¡ You can build a counter by connecting flip-flops to each other. There are two standard ways to do this, one of which results in what is called an asynchronous counter, the other resulting in what is called a synchronous counter. See next slide….

Asynchronous versus Synchronous Counters 4 -bit Asynchronous Counter: 4 -bit Synchronous Counter:

Synchronous versus Asynchronous ¡ 1. The synchronous/asynchronous distinction has different meanings: As applied to inputs: A change on a synchronous input doesn’t affect the outputs until the next active clock edge, but a change on an asynchronous input affects the outputs immediately.

Synchronous versus Asynchronous ¡ 2. The synchronous/asynchronous distinction has different meanings: As applied to counters: in a synchronous counter, the outputs can all change at the same instant; but in an asynchronous counter, there’s a brief delay between the changing of the outputs.

Three bit Asynchronous Counter In an asynchronous counter, the clock is applied only to the first stage. Each subsequent stage gets its clock from the previous stage. The asynchronous counter shown is a three-bit counter (also called MOD-8 counter or divide-by-8 counter). It uses J-K flipflops in the toggle mode. HIGH Q 0 J 0 CLK C K 0 Q 1 J 1 C Q 0 K 1 Q 2 J 2 C Q 1 K 2 Waveforms are on the following slide… © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Three bit Asynchronous Counter Notice that the Q 0 output is triggered on the rising edge of the clock signal. The following stage is triggered from Q 0. The rising edge of Q 0 is equivalent to the falling edge of Q 0. The resulting sequence is that of a 3 -bit binary up counter. CLK Q 0 Q 1 Q 2 Note: This idealized timing diagram ignores the propagation delays from one stage to the next. See next slide… © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Propagation Delay Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. For certain applications requiring high clock rates, this is a major disadvantage. Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage. CLK Q 0 Q 1 Q 2 Q 0 is delayed by 1 propagation delay, Q 1 by 2 delays and Q 2 by 3 delays. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Terminology: Modulus and Divide-By HIGH ¡ Q Q J J J As noted on an CLK C C C earlier slide, the Q Q K K K three-bit counter shown here is also called a MOD-8 counter or a divide-by-8 counter. A counter’s modulus is the number of different values it can count through. The example shown has a modulus of 8. (The eight values are 000, 001, 010, 011, 100, 101, 110, 111. ) Also, the signal at Q 2 will have a frequency equal to one-eighth of the incoming clock frequency. That’s why we can call it a divide-by-8 counter. 0 ¡ ¡ 0 0 0 1 1 2 2 Q 2

The 74 LS 93 Asynchronous Counter The 74 LS 93 has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B. The counter can be extended to form a 4 -bit counter by connecting Q 0 to the CLK B input. Two inputs are provided that clear the count. CLK B J 0 CLK A J 1 C K 0 All J and K inputs are connected internally HIGH J 2 J 3 C C C K 1 K 2 K 3 RO (1) RO (2) Q 0 Q 1 Q 2 Q 3 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

A Family of Four-Bit Asynchronous Counter ICs ¡ 7490 Four-bit decade counter (MOD 10) ¡ 7492 Four-bit divide-by-12 counter (MOD 12) ¡ 7493 Four-bit binary counter (MOD 16)

Asynchronous Decade Counter This counter uses a NAND gate to recycle the count sequence to zero after the 1001 state, resulting in a MOD-10 counter (or decade counter). Other truncated sequences can be obtained using a similar technique. CLR HIGH J 0 CLK C K 0 Q 1 J 2 Q 2 J 3 C C C K 1 K 2 K 3 Q 3 Waveforms are on the following slide… © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Asynchronous Decade Counter When Q 1 and Q 3 are HIGH together, the counter is cleared by a “glitch” on the CLR line. CLK Q 0 Q 1 Glitch Q 2 Q 3 CLR Glitch © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

BCD Decoder/Driver A special-purpose decoder is the 7447. This is a BCD-toseven segment display with active LOW outputs. VCC The a-g outputs are designed for much higher current than most devices (hence the word driver in the name). BCD/7 -seg BI/RBO BCD inputs LT LT RBI BI/RBO Outputs to seven segment device 74 LS 47 GND © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

BCD Decoder/Driver Here the 7447 is an connected to an LED seven segment display. Notice the current-limiting resistors, required to prevent overdriving the LED display. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

7447 BCD-to-7 -Segment Decoder/Driver 4 input pins for BCD code. ¡ 7 output pins to control the seven segments of a 7 -segment display. ¡ Also has a lamp test input. ¡ Also a ripple-blanking input and output to suppress leading or trailing zeroes. ¡ Data sheet: 7447 ¡

Review: Asynchronous versus Synchronous Counters 4 -bit Asynchronous Counter (also called ripple counter): 4 -bit Synchronous Counter:

Synchronous Counters In a synchronous counter all flip-flops are clocked together with a common clock pulse. Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes. This 3 -bit binary synchronous counter has the same count sequence as the 3 -bit asynchronous counter shown previously. CLK HIGH Q 0 J 0 C K 0 Q 0 J 1 Q 0 Q 1 J 2 C C K 1 K 2 Q 2 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

A 4 -bit Synchronous Binary Counter The 74 LS 163 is a 4 -bit IC synchronous counter with additional features over a basic counter. It has parallel load, a CLR input, two count enables, and a ripple count output that signals when the count has reached the terminal count. Data inputs D 0 D 1 D 2 D 3 CLR LOAD ENT ENP CLK RCO Q 0 Q 1 Q 2 Q 3 Data outputs Example waveforms are on the next slide… © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

CLR LOAD D 0 Data inputs D 1 D 2 D 3 CLK ENP ENT Q 0 Data outputs Q 1 Q 2 Q 3 RCO 12 13 14 15 0 Count Clear 1 2 Inhibit Preset © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

A Family of Four-Bit Synchronous Counter ICs ¡ 74160 and 74162: Four-bit synchronous decade counters (MOD 10) l ¡ These two are the same as each other except that 74160 has asynchronous clear, while 74162 has synchronous clear. 74161 and 74163: Four-bit synchronous binary counters (MOD 16) l These two are the same as each other except that 74161 has asynchronous clear, while 74163 has synchronous clear.

Up/Down Synchronous Counters The 74 HC 190 is a high speed CMOS synchronous up/down decade (MOD-10) counter with parallel load capability. It also has a active LOW ripple clock output (RCO) and a MAX/MIN output when the terminal count is reached. D 0 D 1 D 2 D 3 Data inputs 74 HC 190 CTEN D/U LOAD CLK MAX/MIN CTR DIV 10 RCO C Q 0 Q 1 Q 2 Q 3 Data outputs D 0 D 1 D 2 D 3 Data inputs 74 HC 191 The 74 HC 191 has the same inputs and outputs but is a synchronous up/down binary (MOD-16) counter. CTEN D/U LOAD CLK MAX/MIN CTR DIV 16 C RCO Q 0 Q 1 Q 2 Q 3 Data outputs © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

A Family of Four-Bit Up/Down Synchronous Counter ICs ¡ 74190 Four-bit up/down decade counter (MOD 10) ¡ 74191 Four-bit up/down binary counter (MOD 16)

Cascading Counters ¡ ¡ ¡ Most counter chips are 4 -bit counters, with a modulus of 16 or less. To get larger moduli, you cascade two or more counter chips together. When you cascade counters, their moduli multiply, not add. l ¡ Example: If you cascade a MOD-10 counter with a MOD-16 counter, you get a MOD-160 counter. The connections for cascading counters differ depending on whether you’re using asynchronous counters or synchronous counters.

Cascading asynchronous counters © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Cascading Synchronous Counters ¡ ¡ ¡ For cascading, most synchronous counter chips have one or more enable input pins and one or more terminal-count output pins. General idea: one chip’s terminal-count output drives the next chip’s enable input. (See next slide). These pins go by various names such as : l l ¡ CTEN, CEN, ENT, ENP, G for the enable inputs TC, CO, RCO, MAX/MIN for the terminalcount outputs. Also, depending on the chip, these pins may be active-high or active-low, so you may need to insert an inverter.

Cascading synchronous counters For synchronous IC counters, the next counter is enabled only when the terminal count of the previous stage is reached. HIGH Counter 2 Counter 1 CTEN TC CTEN CTR DIV 16 CLK C fout TC CTR DIV 16 Q 0 Q 1 Q 2 Q 3 C Q 0 Q 1 Q 2 Q 3 fin a) What is the modulus of these cascaded counters? b) If fin =100 k. Hz, what is fout? a) Each counter divides the frequency by 16. Thus the modulus is 162 = 256. b) The output frequency is 100 k. Hz/256 = 391 Hz © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved