ECE 353 Introduction to Microprocessor Systems Week 3

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ECE 353 Introduction to Microprocessor Systems Week 3 Michael G. Morrow, P. E.

ECE 353 Introduction to Microprocessor Systems Week 3 Michael G. Morrow, P. E.

Objectives 80 C 188 EB Organization (continued) n n n Segmentation Reset Processing Programmer’s

Objectives 80 C 188 EB Organization (continued) n n n Segmentation Reset Processing Programmer’s Model 80 C 188 EB Machine Language 80 C 188 EB Assembly Language and Assemblers 80 C 188 EB Debuggers

80 C 188 EB Architecture

80 C 188 EB Architecture

Segmented Memory Architecture Memory Segmentation n n Logical vs. Physical Addresses Segment Organization w

Segmented Memory Architecture Memory Segmentation n n Logical vs. Physical Addresses Segment Organization w Topologies n n n Disjoint Overlapping Identical Physical Address Generation Advantages Disadvantages

80 C 188 EB Implementation

80 C 188 EB Implementation

80 C 188 EB Programmer’s Model

80 C 188 EB Programmer’s Model

Programming Languages n n n HLL Assembly Language Machine Language Instructions n n 1

Programming Languages n n n HLL Assembly Language Machine Language Instructions n n 1 – 6 bytes in length Encoding

Assembler Primer Assembler Types n n Native Assembler Cross Assembler General Instruction Syntax Instruction

Assembler Primer Assembler Types n n Native Assembler Cross Assembler General Instruction Syntax Instruction Examples Assembler Functions n n n Syntax checking Offset calculation Encoding to machine code

Example Program Hardware

Example Program Hardware

Source Code File. 186 SWITCHES LEDS equ ; use 80186 instructions 1234 h 5678

Source Code File. 186 SWITCHES LEDS equ ; use 80186 instructions 1234 h 5678 h ; define symbols assume cs: code ; establish CS addressability code segment ; start of code segment main: mov in not mov out jmp ; load switch port address ; read switches ; switch off turns LED on ; load LED port address ; write to LED port ; and repeat indefinitely code ends end dx, SWITCHES al, dx al dx, LEDS dx, al main ; end of code segment main ; code entry point is at main

Assembler Listing File (page 1) Turbo Assembler 1 2 3 4 5 6 7

Assembler Listing File (page 1) Turbo Assembler 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Version 4. 1 09/12/01 08: 49: 11 . 186 =1234 =5678 0000 0003 0004 0006 0009 000 A 000 C BA EC F 6 BA EE EB 1234 D 0 5678 F 4 Page 1 week 3. ASM ; use 80186 instructions SWITCHES LEDS equ 1234 h 5678 h ; define symbols assume cs: code ; establish CS addressability code segment ; start of code segment main: in not mov out jmp mov dx, SWITCHES al, dx al dx, LEDS dx, al main ; load switch port address ; read switches ; SW=1 --> LED on ; load LED port address ; write to LED port ; and repeat indefinitely code ends end main ; end of code segment ; code entry point is at main

Assembler Listing File (page 2) Turbo Assembler Symbol Table Version 4. 1 09/12/01 08:

Assembler Listing File (page 2) Turbo Assembler Symbol Table Version 4. 1 09/12/01 08: 49: 11 Symbol Name Type Value ? ? DATE ? ? FILENAME ? ? TIME ? ? VERSION @CPU @CURSEG @FILENAME @WORDSIZE LEDS MAIN SWITCHES Text "09/12/01" Text "week 3 " Text "08: 49: 11" Number 040 A Text 0103 H Text CODE Text WEEK 3 Text 2 Number 5678 Near CODE: 0000 Number 1234 Groups & Segments Bit Size Align Combine Class CODE 16 none 000 C Para Page 2

Code Generation Process

Code Generation Process

Intel Hex Record Format : 020000021000 EC : 0 C 000000 BA 3412 ECF

Intel Hex Record Format : 020000021000 EC : 0 C 000000 BA 3412 ECF 6 D 0 BA 7856 EEEBF 4 ED : 00000001 FF Record Load Address Record Data Mark Length or 0000 Type Checksum Record Description : 02 0000 02 1000 EC : 0 C 0000 00 : 02 0000 01 BA 3412 ECF 6 D 0 BA 78 ED 56 EEEBF 4 FF Extended address record Data record End-of-file record Disassembling the data record payload. BA 3412(mov dx, 1234 h)EC(in al, dx)F 6 D 0(not al) BA 7856(mov dx, 5678 h)EE(out dx, al)EBF 4(jmp – 12)

Borland Development Tools

Borland Development Tools

Debugger Primer So, why is it called a bug, anyway? Terminology Typical Debugger Operation

Debugger Primer So, why is it called a bug, anyway? Terminology Typical Debugger Operation Debugging Tools n n Software Hardware Comparison of Debugging Tools

Paradigm C++ Demonstration Paradigm C++ (PCPP) is used in ECE 315 PCPP is an

Paradigm C++ Demonstration Paradigm C++ (PCPP) is used in ECE 315 PCPP is an integrated development environment (IDE) n n Code generation Debugging Code Development Tips Use structured programming methods / no spaghetti code. Use descriptive symbols and names. Write comments as you go. When fixing assembler errors, fix only the top one or two and re-assemble – a lot of the later errors may be due to the first few. w When debugging, verify what the registers are loaded with as compared to what you think they should be loaded with. w w

Instruction Decoding Exercise The following memory dump was obtained from an 80 C 188

Instruction Decoding Exercise The following memory dump was obtained from an 80 C 188 EB-based system CS: 0013 is a valid instruction Decode the memory data to determine the instructions that were assembled to produce it. CS: 0013 B 0 12 BA 34 12 FE C 7 EB F 7

Instruction Decoding Solution 16 17 18 19 000 A 000 C 000 F 0011

Instruction Decoding Solution 16 17 18 19 000 A 000 C 000 F 0011 B 0 12 BA 1234 FE C 7 EB F 7 Target: mov inc jmp al, 12 h dx, 1234 h bh Target

Wrapping Up Homework #2 due Friday 9/28

Wrapping Up Homework #2 due Friday 9/28

80 C 188 EB Instruction Encoding Byte 1 OPCODE Byte 2 D W MOD

80 C 188 EB Instruction Encoding Byte 1 OPCODE Byte 2 D W MOD REG Byte 3 Byte 4 Byte 5 Byte 6 LOW DISP/DATA HIGH DISP/DATA LOW DATA HIGH DATA R/M Register operand/registers to use in EA calculation Register operand/extension of opcode Register mode/memory mode with displacement length Word/byte operation Direction is to register/direction is from register Operation (instruction) code [opcode]

JMP Instruction Encoding

JMP Instruction Encoding

INC Instruction Encoding

INC Instruction Encoding

Debugging Tools

Debugging Tools

Disjoint Segments 00000 h CS DS SS FFFFFh

Disjoint Segments 00000 h CS DS SS FFFFFh

00000 h Overlapping Segments CS DS SS FFFFFh

00000 h Overlapping Segments CS DS SS FFFFFh

Identical Segments 00000 h CS DS SS FFFFFh

Identical Segments 00000 h CS DS SS FFFFFh