Digital Logic Design Slides By ADEELA MUSTAFA Topics
Digital Logic Design Slides By ADEELA MUSTAFA
Topics 9 s-Complement with fraction Part. Short way of taking Complement. Subtraction of numbers using Complements. Signed binary numbers. Coding Scheme. Registers.
Subtraction With Complements The subtraction of two n- digits unsigned numbers M – N in base r can be done as follows:
Subtraction With Complements Subtraction with 10 s-Complement-: 1. M = (72532)10 N = (3250)10 Subtraction with 2 s-Complement: 1. M = (1010100)2 N = (1000011)2
Subtraction With Complements Subtraction Using 2 s-Complement-: 1. M = (110010)2 N = (110100)2 Subtraction Using 1 s-Complement: 1. M = (110101)2 N = (100101)2 Subtraction Using 1 s-Complement: 1. M = (101011)2 N = (111001)2
Subtraction With Complements Subtraction Using 9 s-Complement-: 1. M = (215)10 N = (155)10
Signed binary numbers To represent negative integers, we need a notation for negative values. It is customary to represent the sign with a bit placed in the leftmost position of the number. The convention is to make the sign bit 0 for positive and 1 for negative.
Coding scheme BCD Code 2421 Code ASCII Code
Binary Codes Error-Detecting Code 1. To detect errors in data communication and processing, an eighth bit is sometimes added to the ASCII character to indicate its parity. 2. A parity bit is an extra bit included with a message to make the total number of 1's either even or odd. Example: Consider the following two characters and their even and odd parity:
Binary Storage & Registers is a small set of data holding places that are part of a computer processor, may hold a computer instruction a storage address or any kind of data(such as bit sequence). In some computer design smaller registers for example half registers for shorter instruction depend on processor design language rules and may be numbers
- Slides: 14