UW Engineering DOM Studies Kael Hanson University of

























- Slides: 25
UW Engineering DOM Studies Kael Hanson University of Wisconsin – Madison LBNL DOM Workshop 23 July 2003 LBNL DOM Workshop
What Testing was Done? • Guiding principle “Attempt to carry out measurements and see how DOM behaves as a data acquisition platform then follow our noses. ” • Initial measurements desired: – Phototube gain – Peak-to-valley – Phototube noise (not yet /w/ DOM) • These measurements implied a priori characterization of DOM analog F. E. • Summary of measurements captured in Engineering DOM Tests document. 23 July 2003 LBNL DOM Workshop 2
DOMs Under Test (DUTs) • UW now has 12 DOM-MBs: – 5 in ‘active’ DOMs (XE 3 P 0001 -0005) – 6 in DOMs awaiting testing – 1 DOMMB in use by NK for HV base tests • 2 DOMMBs returned to LBNL because of hardware problems: – 1 flash RAM failure – 1 CPLD failure (could not program) 23 July 2003 LBNL DOM Workshop 3
DUT Configurations • Currently all 4 above DOMs running in chest freezer at PSL • XE 3 P 0003 is in freezer at Chamberlin undergoing analog tests • Full DOM Work-in-Progress table maintained by Jim Hoffman 23 July 2003 LBNL DOM Workshop 4
ATWD Pedestal Study • Purpose – Monitor system electronic noise – ATWD gain calibration • Procedure – Set ambient temperature to -20 ºC, … – Set FE bias to various levels – Acquire CPU-triggered ATWD shots 23 July 2003 LBNL DOM Workshop 5
FE Gain – ATWD Channel 0 Clamping amplifier in ATWD ch 0 introduces nonlinearity in analog FE! 23 July 2003 LBNL DOM Workshop 6
FE Gain – ATWD Channel 1 No clamping amp – linear but ATWD overflows around 1 V – incorrect ATWD tuning parameters here or intentional behavior? 23 July 2003 LBNL DOM Workshop 7
FE Pedestal/Gain Calibration Proposal • If you take delta between 5 th and 1 st curves on previous plot, you would naively expect a flat line. • Resulting line is not flat – features persist – do we need separate gain calibration for each ATWD bin? 23 July 2003 Is this subscript necessary? I LBNL DOM Workshop 8
Pedestal Noise – ISEG DOM 718 F PMT HV turned off! max(abs(wfd-ped)) 23 July 2003 LBNL DOM Workshop 9
ATWD Pedestal Noise (2) • HV base turned off but ISEG base (718 F) just disables HV – power not turned off to base. Disconnecting HV ribbon lowers noise somewhat. • Oddly enough, Ch 1 shows about same level of noise – would expect 4 x less scaling with opamp gain. 23 July 2003 LBNL DOM Workshop 10
Pedestal Noise – ISEG DOM 7 DAC (ISEG base /w/ no ground wire) 23 July 2003 LBNL DOM Workshop 11
Pedestal Noise – EMCO DOM 71 DB 23 July 2003 LBNL DOM Workshop 12
Floating Baseline? • Tried to test noise with HV on/off but run into problem of wobbling ATWD baseline and odd undershoot at pulse beginning (RHS). • (See next page) overall stability of pedestal on 2 hr timescale OK /w/ HV off but HV on causes large rms and drift. 23 July 2003 LBNL DOM Workshop 13
ATWD Drift vs. Time NO HV HV ON Approx 2 hr. run time 23 July 2003 LBNL DOM Workshop 14
Summary on Pedestal Testing • Significant noise in FE seems due to HV base (no noise seen in DOMMB tests? ). Of options EMCO/ISEG, latter produces clearly visible hash in FE while former is clean. • Clamping amp nonlinearity significant. Can we tune this away or are we stuck with it? Do we really want to put a clamping amp on any more channels? • ATWD channel 1 overflows at about 1 V input (50 pe) – again, is this a tuning problem? • Is ATWD FE characterization simply a pedestal fingerprint or do we need more calibration knobs such as individual ATWD bin pedestals and gains. 23 July 2003 LBNL DOM Workshop 15
Pulser Tests • Purpose – Calibrate op-amp gains – SPE/MPE discriminator studies • Procedure – Disable HV – Set internal pulser amp to 1/3 pe, 1 pe, … – Do discriminator sweep (FSCAN) – Acquire pulser waveforms 23 July 2003 LBNL DOM Workshop 16
Pulser Discriminator 23 July 2003 LBNL DOM Workshop 17
Pulser Waveforms • Unable to acquire pulser waveforms with synchronous pulser trigger – advertised in FPGA register level docs but either I called incorrectly or problem at FPGA • This type of trigger – synch with FE pulser, LED flasherboard required for some tests. 23 July 2003 LBNL DOM Workshop 18
SPE Discriminator Scan – PMT Pulses Input (71 DB) 23 July 2003 LBNL DOM Workshop 19
SPE Waveforms CH 0 CH 2 CH 1 23 July 2003 LBNL DOM Workshop 20
SPE Waveforms (2) • Presence of HV again causes drift of front-end baseline. • This may be due to ATWD overvoltage – ATWD channel 1 can saturate – ATWD channel 2 seems OK – small drift but probably functional – Why is ATWD channel 0, protected by clamping amplifier, having problems? • Current situation with drifting baselines makes analysis of ch 0/ch 1 waveforms very tricky – hope we can alter the clamping voltage to workaround – need information on this system. 23 July 2003 LBNL DOM Workshop 21
Gain and P/V Measurement – DOM 0001 -3 C 62 -71 BD 23 July 2003 LBNL DOM Workshop 22
Cheap P/V & Gain Analysis • Used ATWD ch 2 because of baseline wobble – gain of this channel is 2/3× so had to crank HV up to 1600, 1800, 2000 V. • Clear P/V appears at 2000 V (apx. 2. 2: 1) • Assuming ATWD gain is 1 m. V/count, FE gain is 2/3×, the peak occurs around 40 m. V – resulting in gain of about 5 × 107 – this just makes target! 23 July 2003 LBNL DOM Workshop 23
Signal Frequency Analysis 23 July 2003 LBNL DOM Workshop 24
Conclusions • Noise on ISEG HV base is potential trouble – analog tests indicate that level is less than 1 m. V p-p but really need to understand characteristics after FE op-amps. • Several issues with ATWD-captured waveforms: – ‘startup’ bug: 1 st sample after several seconds idle is corrupted – this is more annoying than problematic – Crosstalk from clock when mux’ed into channel 3 – OK once AG explained the problem and the fix. However, crosstalk from ch 0 to ch 1, ch 2 potential problem. Do we test? – Clamping amplifier causes log rolloff of channel 0 – Saturated ATWD inputs cause sizable baseline drift • ATWD channel 0 gain seems a bit high – 16 x implies approx 100 m. V spe, about 100 ATWD counts. Could probably reduce gain by factor of 2, perhaps up to 4. 23 July 2003 LBNL DOM Workshop 25

























