SRAM Arrays ECE 352 Digital System Fundamentals SRAM

SRAM Arrays ECE 352 Digital System Fundamentals SRAM Arrays 1

SRAM Arrays SRAM Device Characteristics 2 • • • The device capacity is the total number of bits stored The width is number of bits stored at each location The depth is the number of locations that it contains • Example: • The 64 k × 8 device below has a capacity of 512 kbits indicates output is tristated if CS=0

SRAM Arrays of SRAM Devices 3 • Can build an m × n SRAM memory system we need out of multiple, smaller SRAM devices • Key ideas: • Use multiple devices to create required memory capacity • Distribute words (or parts of words) across several devices • Need to be able to access all bits of the correct word at once

Increasing Width: 64 k × 16 Array • The available 64 k × 8 SRAM devices are deep enough, but they are not wide enough DI[15: 0] DO[15: 0] SRAM Arrays A[15: 0] DI[15: 8] A[15: 0] DO[15: 8] CS Each SRAM device stores half of each word. DI[7: 0] A[15: 0] DO[7: 0] CS CS 4

Increasing Depth: 128 k × 8 Array • The available 64 k × 8 SRAM devices are wide enough, but they are not deep enough DI[7: 0] DO[7: 0] SRAM Arrays A[16: 0] DI[7: 0] A[15: 0] DO[7: 0] CS 1 A[16] CS CS 1 CS 0 addresses 0 x 10000 -0 x 1 FFFF DI[7: 0] A[15: 0] DO[7: 0] CS 0 CS 5 addresses 0 x 00000 -0 x 0 FFFF

Increasing Depth: 128 k × 8 Array • The available 64 k × 8 SRAM devices are wide enough, but they are not deep enough DI[7: 0] DO[7: 0] SRAM Arrays A[16: 0] DI[7: 0] A[16: 1] DO[7: 0] CS 1 A[0] CS all odd addresses CS 1 CS 0 DI[7: 0] A[16: 1] DO[7: 0] CS 0 CS 6 all even addresses

Increasing Depth: 256 k × 8 Array • Array capacity now 2 Mb, so requires 4 SRAM devices DI[7: 0] DO[7: 0] DI[7: 0] A[15: 0] SRAM Arrays A[17: 0] CS 3 DI[7: 0] A[15: 0] A[17] A[16] CS CS 3 CS 2 CS 1 CS 0 CS 2 DI[7: 0] A[15: 0] CS 1 CS DI[7: 0] A[15: 0] CS 0 7 DO[7: 0] addresses 0 x 30000 -0 x 3 FFFF DO[7: 0] addresses 0 x 20000 -0 x 2 FFFF DO[7: 0] addresses 0 x 10000 -0 x 1 FFFF DO[7: 0] addresses 0 x 00000 -0 x 0 FFFF

Array Design Example • SRAM Arrays • 8 • • What if we needed to build a 128 K × 16 RAM out of 64 K × 8 RAMs? The total capacity of the array is 128 k × 16 = 2 Mbit Each 64 K x 8 RAM has a capacity of 64 k × 8 = 512 kbit The array will require 2 Mbit / 512 kbit = 4 devices

Example: 128 k × 16 Array DO[15: 0] DI[15: 0] A[16: 0] 64 k x 16 DI[15: 8] A[15: 0] DI[7: 0] A[15: 0] DO[7: 0] SRAM Arrays DO[15: 8] CS 1 64 k x 16 DI[15: 8] A[15: 0] DI[7: 0] A[15: 0] DO[15: 8] CS 0 CS 9 DO[7: 0] CS 0 A[16] CS CS 1 CS 0

Example: 128 k × 16 Array DO[15: 0] DI[15: 0] A[16: 0] 128 k x 8 DI[15: 8] A[15: 0] DI[7: 0] A[15: 0] DO[7: 0] SRAM Arrays DO[15: 8] CS 1 DI[15: 8] A[15: 0] DI[7: 0] A[15: 0] DO[15: 8] CS 0 CS 10 DO[7: 0] CS 0 A[16] CS CS 1 CS 0

SRAM Array Concepts • SRAM Arrays • • 11 The array capacity cannot be greater than the total capacity of the devices in the array Each bit of any array location is stored in one and only one physical location A read from any array address must return the data previously written to that address • Writes must only affect the addressed location Each bit of the output data can only be driven by one device at any time None of array devices should be selected unless the array is selected

SRAM Arrays ECE 352 Digital System Fundamentals SRAM Arrays 12