Pipelining ECE 352 Digital System Fundamentals Pipelining 1

Pipelining ECE 352 Digital System Fundamentals Pipelining 1

Laundry Pipelining Example Pipelining • 2 You could wait for a load to completely finish before you start the next… Four loads in 8 time units Time Units: 0 8 6 4 3 1 7 5 2 Green: done after 2 Purple: done after 4 Orange: done after 6 Blue: done after 8

Laundry Pipelining Example Pipelining • 3 2 -stage pipeline: start new washer load at same time you put first load in dryer • Work on two loads at once, at different stages of completion Four loads in 5 time units Time Units: 0 4 3 1 5 2 Green: done after 2 Purple: done after 3 Orange: done after 4 Blue: done after 5

Laundry Pipelining Example • What does this mean? • If you wash your favorite shirt first, it is not done sooner • But you get approximately twice the amount of laundry done Pipelining in the same time (if doing many loads) 4 Four loads in 5 time units Time Units: 0 4 3 1 5 2 Green: done after 2 Purple: done after 3 Orange: done after 4 Blue: done after 5

Terminology • Pipelining • • Latency • Throughput • The rate at which “results” are produced Laundry Example: • • 5 The length of time it takes for a value ready at the input to propagate to a “result” at the output Unpipelined • • Latency = 2 time units Throughput = 1 result per 2 time units Pipelined • • Latency = 2 time units Throughput = 1 result per time unit Note: throughput ignores startup latency (2 time units until first result produced)

Pipelining Digital Circuits • What can we do to increase it? Increase throughput by still producing one result per clock cycle, but with a shorter tmin How can we decrease tmin and still accomplish the same amount of work? 6 Registers • Registers Pipelining • Original circuit has lower throughput than desired Logic •

Pipelining Digital Circuits 7 Registers Logic Stage 2 Clock rate of modified circuit is limited by longest combinational path between registers, so we want to subdivide as evenly as possible (balance the stages) Registers Logic • Registers Pipelining • Insert registers to subdivide long-latency combinational blocks into two (or more) stages New circuit has a shorter critical path Logic Stage 1 •

Reg Still produces 1 result / cycle PIPELINED Logic • Logic Pipelined with 2 evenlybalanced stages Reg • ORIGINAL Logic Original circuit produces 1 result per cycle Reg • Reg Pipelining Effects tcomb, pipe = (tcomb, orig / 2) tmin, pipe = tpd + tcomb, pipe + ts = tpd + (tcomb, orig / 2) + ts tmin, pipe > (tmin, orig / 2) 8 Pipelined circuit can be clocked faster, but not 2× faster!

Pipelining Effects • • 9 Latency is increased! Logic Reg N stages, so latency is N cycles tmin, pipe is more than tmin, orig / N Logic • • PIPELINED Reg Produce a result once per cycle fmax, pipe is higher than fmax, orig Reg • • ORIGINAL Logic Pipelining • Throughput is increased! Reg • Pipelining is only useful if we can take advantage of throughput increase and can tolerate latency increase • Need to be processing a sequence of data… Diminishing returns as pipeline depth (N) increases

Add Four Values: Non-Pipelined • Pipelining • Calculate tmin =  tpd + t. ADD 1 + t. ADD 2 + ts • All paths in this circuit have the same delay min = 1 × t Calculatency = 1 cycle × tp min latency = 27 ns • The time it takes for input values that are ready in their registers to propagate to output Y A B C 10 = 4 + 10 + 12 + 1 = 27 ns D + t. ADD 1 For these delay values… ts = 1 ns t. ADD 1 = 10 ns tpd = 4 ns t. ADD 2 = 12 ns + Y t. ADD 2 Throughput = 1 result per cycle Max = 1 result / 27 ns = 37 M results / s

Add Four Values: Pipelined • • Calculate tmin =  tpd + max(t. ADD 1,  t. ADD 2) + t. S • Pipelining min = 2 × t min latency = 34 ns Same idea, but remember that the length of each pipeline stage is dictated by the same clock! Calculatency = 2 cycles × tp • A B C 11 Based on the longest path = 4 + max(10,  12) + 1 = 17 ns D + t. ADD 1 t. COMB is the longest of these paths For these delay values… ts = 1 ns t. ADD 1 = 10 ns tpd = 4 ns t. ADD 2 = 12 ns + Y t. ADD 2 Throughput = 1 result per cycle Max = 1 result / 17 ns = 59 M results / s

ts = 1 ns tpd = 4 ns Pipelining Comparison Non-Pipelined • • tmin: 27 ns • tmin: 17 ns Max Throughput: 1 result / cycle = 37 M results / s • Max Throughput: 1 result / cycle = 59 M results / s Minimum Latency: 1 cycle = 1 × tmin = 27 ns • Minimum Latency: 2 cycles = 2 × tmin = 34 ns • A B C 12 t. ADD 1 = 10 ns t. ADD 2 = 12 ns D + t. ADD 1 A + t ADD 2 Y B C D + t. ADD 1 + t ADD 2 Y

Pipelining Summary • Pipelining • • 13 Technique that can increase frequency and throughput at the expense of latency and area If adding pipeline stages, we need to evaluate: Is latency, throughput, or area most important for how that particular circuit will be used? Where should pipeline registers be added? • Clock speed depends on the longest path… Limited by flip-flop ts and tpd (diminishing returns) • There are tricks we can use to mitigate this, but they are beyond the scope of the class….

Pipelining ECE 352 Digital System Fundamentals Pipelining 14