SRAM Generator Satya Nalam SRAM Architecture n SRAM

SRAM Generator - Satya Nalam

SRAM Architecture n SRAM specs n n n n Single bank Capacity – 8 -32 kb Col-mux – 1, 2, 4, 8 #Rows – 8 -512 #Rows and #cols power of 2 Timing block using encounter Schematic/Layout script for tiling each block Wrapper script to generate final SRAM

Design WLs Pre-decode o/p BLs BL PCH CSEL SAE SAPCH Enable Address Rd/Wr Col-muxed BLs SA output EN Data in & out

Schematic Generation n n Can be completely automated Parametrization Use @key in Skill procedures for optional arguments Transistor sizes from optimization result procedure(Uva. Ece. Schematic. Create. Inst. Par. Nand 2(cvid lib. Name cell. Name Iname location intop inbot out VDD VSS @key (lp 0. 06) (wp 0. 20) (ln 0. 060) (wn 0. 20) (m 1))

Schematic Generation n Leaf-cell schematic creation n Bitcells – PDK Decoders – Skill Everything else – Manual, can be replaced by Skill

Layout Generation: WLD 2 WLD 1 WL Drivers • Via-programmed • Staggered for pitchmatching

Layout Generation: Array Termination cells Well taps

Layout Generation: Timing Predecode outputs Design placed and routed by Encounter

Layout Generation: Bitslice CD SA IO IO Staggered for pitch-matching

Layout Generation: Top-level 128 x 64 SRAM Routing through Abutment - Fillers with metal

Summary of useful tips for automation through Skill n n Using procedures – with @key optional arguments Via-programming Staggering for pitch-matching Routing through abutment

Final deliverable n n Completed set of highly parametrized Skill scripts for SRAM schematic and layout generation. Technology and user independent. n n Class-specific work – parametrization of schematic and layout scripts Documentation in progress.