MOORES LAW The Journey Continues Mark Papermaster CTO

MOORE’S LAW + The Journey Continues Mark Papermaster CTO & SVP, Technology & Engineering 1 | D 60: BREAKTHROUGH TECHNOLOGY: PAST, PRESENT, FUTURE | SEPTEMBER 5, 2018 |

DEMAND FOR BETTER EXPERIENCES VOICE, GESTURE, FACE RECOGNITION SUPER HIGH RESOLUTION DISPLAYS VR, AR HUGE DEMAND FOR MORE COMPUTE BIG DATA ANALYTICS HIGH-PERFORMANCE COMPUTING 2 | D 60: BREAKTHROUGH TECHNOLOGY: PAST, PRESENT, FUTURE | SEPTEMBER 5, 2018 | MACHINE LEARNING

GPU & CPU PERFORMANCE TRENDS GPU SINGLE PRECISION FLOATING POINT OPERATIONS PER SECOND TREND Throughput Performance Ratio Single Precision GFLOPS 100, 000 GF ars 1 ye ry 2. e 2 X ev 10, 000 GF SPECINT®_RATE 2006 2 P SERVER PERFORMANCE TREND OVER TIME 1, 000 GF 100 X rs ea y 4. ry 2 e v Xe 2 10 X 1 X 100 GF 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 2008 CONSISTENT AND EXPONENTIAL GPU/CPU PERFORMANCE GAINS 3 | D 60: BREAKTHROUGH TECHNOLOGY: PAST, PRESENT, FUTURE | SEPTEMBER 5, 2018 | See Endnotes

SYSTEM-LEVEL PERFORMANCE/WATT IMPROVING AT THE SAME RATE PERFORMANCE-PER-WATT TREND OVER TIME IN SERVER CPUS Spec Power® Overall Score Ratio 100 ry 2. 4 y e v e X 2 ears 10 1 1899 1900 PERFORMANCE GAINS HAVE BEEN SYSTEM LEVEL POWER-NEUTRAL 4 | D 60: BREAKTHROUGH TECHNOLOGY: PAST, PRESENT, FUTURE | SEPTEMBER 5, 2018 | See Endnotes

MOORE’S LAW IS SLOWING 107 50 YEARS OF MICROPROCESSOR TREND DATA More transistors more power efficiency 106 105 104 Less frequency gain per node 103 102 101 Transistors (thousands) 100 1970 Frequency (MHz) 1980 1990 5 | D 60: BREAKTHROUGH TECHNOLOGY: PAST, PRESENT, FUTURE | SEPTEMBER 5, 2018 | 2000 2010 2020 2030 See Endnotes

MOORE’S LAW SLOWS WHILE COSTS CONTINUE TO INCREASE COST PER YIELDED MM 2 FOR A 250 MM 2 DIE Normalized Cost/yielded mm 5. 00 4. 00 3. 00 2. 00 1. 00 45 nm 32 nm 28 nm 20 nm 14/16 nm 7 nm INCREASING DIE SIZES ARE ECONOMICALLY PROBLEMATIC 6 | D 60: BREAKTHROUGH TECHNOLOGY: PAST, PRESENT, FUTURE | SEPTEMBER 5, 2018 | Source: AMD

WELCOME TO MOORE’S LAW + INTEGRATION SYSTEM DESIGN SOFTWARE Multi-Chip Architectures Accelerators Compilers 2/2. 5/3 D Packaging New Memory Architectures Open Source Libraries Scalable Fabrics Industry Standard Interconnect Frameworks 7 | D 60: BREAKTHROUGH TECHNOLOGY: PAST, PRESENT, FUTURE | SEPTEMBER 5, 2018 |

ACCELERATING THE EXPONENTIAL A BETTER FUTURE DEPENDS ON IMPROVING COMPUTATION EFFICIENCY NEW APPROACHES NEW ARCHITECTURE IMPROVEMENT OPPORTUNITIES FOR THE NEXT DECADE Log Scale System Performance/Watt s . 4 2 / ar e y 3 D Stacking X >2 Novel Memory rs ea y. 4 Software X/2 2 Accelerators Multi-Chip Architecture 2007 2017 2027 8 | D 60: BREAKTHROUGH TECHNOLOGY: PAST, PRESENT, FUTURE | SEPTEMBER 5, 2018 | Process Technology See Endnotes

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ENDNOTES Slides 3, 4, 5, 6, 8 Lisa T. Su, Samuel Naffziger, and Mark Papermaster, “Multi-Chip Technologies to Unleash Computing Performance Gains over the Next Decade, ” IEDM Conference 2017. Slide 5: Original data up to the year 2010 collected and plotted by M. Horowitz, F Labonte O. Shacham, K. Olukotun, L. Hammond, and C. Batten. New plot and data collected for 2010 -2015 by K. Rupp. https: //www. karlrupp. net/2015/06/40 -years-of-microprocessor-trend-data/ 11 | D 60: BREAKTHROUGH TECHNOLOGY: PAST, PRESENT, FUTURE | SEPTEMBER 5, 2018 |