IAY 0600 Digital Systems Design Digitaalssteemide disain Course

IAY 0600 Digital Systems Design Digitaalsüsteemide disain Course Overview Alexander Sudnitson Tallinn University of Technology

Administrative Aleksander Sudnitsõn (Alexander Sudnitson) Department of Computer Engineering (Arvutitehnika instituut) Associate Professor (dotsent) ICT-503 aleksander. sudnitson@ttu. ee Tel. +372 5092356 www. pld. ttu. ee/~alsu 2

Course resources www. pld. ttu. ee/~alsu IAY 0600 Digital Systems Design (LECTURES) Digitaalsüsteemide disain IAY 0600 l Digital Systems Design (WORKSHOPS) Digitaalsüsteemide disain (LABS) 3

Lectures Lecture: Wednesday 14. 00 - 15. 30 http: //ati. ttu. ee/~alsu/IAY 0600. html 4

Labs A. Wednesday 16. 00 - 17. 30 B. Wednesday 17. 45 - 19. 15 Assistant: research scientist, Dimitri Mihhajlov, Ph. D Technical Assistant: early stage researcher Artjom Rjabov 5

Labs http: //ati. ttu. ee/~alsu/IAY 0600 l. html IAY 0600 l 6

Grading To stimulate the student’s activity a project-based evaluation approach is adopted. Grading consists of control of knowledge in examinations and of the demonstration of the projects and the quality of a written reports (30 points in final grade for doing compulsary labs, up to 90 points in final grade for doing optional labs). “LEARN BY DOING” Learning By Example Using VHDL (with FPGA Evaluation Boards) 7

Passing a Lab Every completed experiment (project) must be presented to Assistant (D. Mihhailov), who will evaluate student’s results and effort Each lab is passed in three steps: Step 1: Visual demonstration Step 2: Submission of the report Step 3: Defence/discussion of the report Labs can be done either individually, or in teams of two. Note, that in case of teamwork Step 2 and Step 3 MUST be done by each team member separately. 8

Compulsory Labs labelled “compulsory” form the basic core of the course. In order to pass the course these labs MUST be completed within the deadline. Passing all compulsory labs yields the minimum positive final grade and allows possibility to attend the exam. • • Comparator Adder Parameterizable Adder Shift Register 9

Optional Labs labelled “optional” are more advanced labs that are not required to be completed in order to pass the course. However, each successfully passed optional lab increases the final grade (up to the maximum for doing all optional labs). • • • FSM Greatest Common Divisor LFSR Creeping Line RISC Processor 10

Labs Xilinx FPGA Tools The laboratory assignments are done using the Xilinx ISE Software and Vivado. simulation synthesis implementation Digilent Nexys 3 and Zed. Board FPGA Boards 11

Course goals ü to elaborate knowledge of the design process from design description in VHDL through functional simulation, synthesis, timing simulation, and PLD (FPGA) programming; ü to gain experience in designing and verifying digital systems using synthesis and simulation tools; ü to provide students theory and practice of rapid prototyping of digital systems in a laboratory environment; 12

Outcomes üto proceed from a digital system description in VHDL to its implementation in a PLD (FPGA) using of a number of computer-aided design software tools; üto understand how to interpret design tool outputs in evaluating alternative system designs for a specific set of requirements, and how to use the knowledge gained to improve the design. 13

Why is this course worth taking? • VHDL for synthesis: one of the most sought-after skills • knowledge of state-of-the-art tools used in the industry • knowledge of the modern FPGA & ASIC technologies • unique knowledge and practical skills that make you competitive on the job market

Main topics ü ü The course is based on the development of a real-world projects and case studies Synthesizable VHDL Digital systems design methodology using VHDL and PLD (FPGA) FPGAs as means for building reconfigurable systems Rapid prototyping of digital systems. 15

Slides http: //ati. ttu. ee/~alsu/IAY 0600. html Lecture slides (to be published before each lecture). Auxiliary material: Digital Systems Modelling and Synthesis http: //www. ati. ttu. ee/IAY 0340/ 16

Textbooks Short K. L. VHDL for Engineers, Pearson Education, Inc. , 2009, 2013. Chu P. P. FPGA Prototyping Using VHDL Examples: Xilinx Spartan-3 Version, Jonh, Willey & Sons, 2008. Pedroni V. A. Circuit Design and Simulation with VHDL, Massachusetts Institute of Technology, 2010. Skljarov V. , Skliarova I. , Sudnitson A. Design of FPGAbased Circuits using Hierarchical Finite State Machines. TUT Press, Tallinn, 2012, 240 p. Sarah L. Harris & David M. Harris, "Digital Design and Computer Architecture“, Elsevier, 2016. 17