FPGAs and obsolescence mitigation EIROforum School of Instrumentation

FPGAs and obsolescence mitigation EIROforum School of Instrumentation 15 -19 June 2015 Dr. Ignacio Molina European Southern Observatory

Outline Background: from simple programmable logic devices to FPGAs Basic architecture of the Xilinx Spartan 6 Example FPGA-based implementation: obsolescence mitigation ESI 2015 2

Physical implementation alternatives Standard SSI/MSI LSI/VLSI Gates Multiplexers Decoders Arithmetic Registers Counters ASIC PLD SPLD RAM, ROM Microprocessors Microcontrolers DSP CPLD FPGA Semi-Custom PROM GAL (S/M/L/VL)SI: (Small/Medium/Large/Very Large) Scale of Integration (RA/RO/PRO)M: (Random Access/Read Only/Programmable Read Only) memory (S/C)PLD: (Simple/Complex) Programmable Logic Device DSP: Digital Signal Processor GAL: Generic Array Logic FPGA: Field Programmable Gate Array ASIC: Application-Specific Integrated Circuit ESI 2015 3 Full-Custom

Programmable Logic Device (PLD) Simple PLD (SPLD): Ø Legacy MSI functional bocks: mux/demux, coders/decoders, counters, registers, etc configurable functions (PLD) Ø Depending upon manufacturer: GAL (Generic Array Logic), or Versatile Programmable Array Logic (PAL) Device Ø Main manufacturers: Lattice, Atmel, Philips, AMD, Cypress, Texas Instruments ESI 2015 4

PLD Architecture GAL 22 V 10: Ø 11 dedicated input pins, 10 I/O pins Ø Output enable (tri-state), reset/preset for flip-flops (FFs) Ø Clock Pin (CP) for FFs / Input pin Ø Programmable AND matrix: product terms Ø Output Logic Macrocell (OLMC): combinational / register ESI 2015 5

GAL 22 V 10 architecture & OLMC f 1 = x 1*x 2*/x 3+/x 1+x 2+x 3 ESI 2015 6

Complex PLD (CPLD) vs SPLD Multiple SPLDs in the same silicon die sharing interconnection resources: Ø Function block: SPLD Ø On each CPLD macrocell it can be increased: • The number of product terms (addends per OR ) • The number of AND inputs Ø More complex designs Ø Main manufacturers: • Altera, Xilinx, Atmel, Cypress, Lattice Ø Xilinx family examples: • Coolrunner: XPLA 3 (3, 3 V), II (1, 8 V) • XC 9500: standard (5 V), XL (3, 3 V), XV (2, 5 V) Ø Different voltages, packages, I/O standards, speeds ESI 2015 7

Field Programmable Gate Array (FPGA) In-field / in-place programmable: reconfigured by the designer (no need from manufacturer). Ø High performance and integration density Ø Rapid prototyping and production Ø Main manufacturers: Xilinx, Altera (Intel), Lattice, Actel, Quicklogic (CSSP: Customer Specific Standard Products) Programmable logic cell Programmable I/O block Programmable interconnection ESI 2015 8

Xilinx Spartan 6 family ESI 2015 9

CLBs, Slices and LUTs Configurable Logic Block (CLB): each consisting of two slices (each containing four LUTs) LUT (Look-Up Table): logic function generator Example 3 -input LUT a 3 -input y b c LUT ESI 2015 abc y 000 001 010 011 100 101 110 111 0 1 0 1 10

SLICEM and LUT 6: Simplified view ESI 2015 11

I/O resources Basic IOB diagram • Single-ended I/O standards: LVCMOS, LVTTL, HSTL, SSTL, PCI • Differential I/O standards: LVDS, RSDS, TMDS, Differential HSTL and SSTL I/O tile I/O banks ESI 2015 12

Clock management: PLL, DCM Clock Management Tile (CMT): Ø One PLL (Phase-Locked Loop) Ø Two DCMs (Digital Clock Manager): • • Eliminate skew Phase shifting Multiply/divide incoming clock frequency Conditioning, rebuffering, jitter filtering Clock at FF 1 Clock at FF 2 Skew The DLL (Delay-Locked Loop) provides deskew pk-pk jitter in ps Ideal clock edge DFS (Digital frequency synthesizer Jitter histogram Jitter ESI 2015 13

Clocking resources Four types of connections: Ø Global clock input pads (GCLK) Ø Global clock multiplexers (BUFG, BUFGMUX) Ø I/O clock buffers (BUFIO 2, BUFIO 2_2 CLK, BUFPLL) Ø Horizontal clock routing buffers (BUFH) Two types of clock networks: Ø Global clock network providing low-skew clock routing to the FPGA logic resources Ø I/O regional clock networks providing high-performance low-skew clocking to the Select. IO logic resources ESI 2015 14

Global clocking infrastructure Driven by 16 BUFGMUX, located in the center of the device The 16 BUFGMUX fed from: bank clocks inputs, FPGA logic interconnect and/or PLL/DCM ESI 2015 15

BUFH, BUFMUX and I/O clocks BUFH routing BUFGMUX connections I/O clocks in an I/O bank ESI 2015 16

Clock pin layout ESI 2015 17

DSP slice, block RAM, Gigabit transceiver 35 x 35 multiplier from cascaded slices ESI 2015 18

Block RAM, Gigabit transceiver Block RAM: Ø Ø Up to 18 K bits of data 2 x 9 Kb or one 18 Kb Single or dual-port Different organizations GTP (Gigabit Transceiver, low-Power): Ø Ø ESI 2015 Ultra-fast data transmission between ICs, backplanes, long distances Combined transmitter and receiver on each GTP Up to 3. 125 Gb/s, 2 -8 GTPs Transmitter and receiver parallel-to-serial / serial-to-parallel converters with separate PLLs 19

Spartan-6 configuration RAM based devices (embedded CMOS configuration latches or CCLs) A bitstream must be loaded into internal memory Nonvolatile memory, u. P, DSP, u. C, PC Programming interface, special configuration pins Configuration modes: Ø JTAG (Joint Test Action Group) interface Ø Serial or Parallel ESI 2015 20

Available I/O pin/device/package combinations ESI 2015 21

Xilinx Spartan 6 family (revisited) ESI 2015 22

FPGA design flow System design I/O assignment: package, performance RTL (Register Transfer Level) synthesis Place & Route ESI 2015 23

Hardware Description Languages VHDL (Very High Speed Integrated Circuit Hardware Description Language) vs Verilog: Ø No relevant differences in performance Ø Choice: personal preferences, available tools/models, commercial, marketing issues Ø Both are IEEE standards Ø Verilog: inspired on C language Design tools: Ø Xilinx: ISE / VIVADO Ø Altera: Quartus II ESI 2015 24

Other devices, applications Xilinx: Ø FPGA: Spartan-6, Artix, Kintex, Virtex Ø Zynq (So. C) Ø 3 D IC Altera: Ø FPGA: MAX 10 Ø FPGA/So. C: Stratix, Arria, Cyclone Applications: automotive, aerospace, consumer electronics, defense, industrial, etc Many educational kits! Spartan-6 LX 9 Micro. Board ESI 2015 25

Case application: obsolescence mitigation Obsolete motor controller board: Ø Ø Ø Ø ESI 2015 VME (Versa Module Europe) module Installed on many instruments (more than 100 boards) No further support from manufacturer Many old PLDs CPU: Motorola MC 68000 Peripheral Controller: MC 68901 Discrete RAM, ROM ICs Schematics in hard print 26

Motor controller with FPGA: feasibility test Soft cores for u. P and peripheral controller: Ø Open (SUSKA project: http: //www. experiment-s. de/en) Ø IP cores: i. e. , Millogic MC 68 SEC 000 still in production (Freescale) Binaries (ROM content) for CPU program available! VME bus buffers (interface, level translators) required PLDs: Ø 8 PLDs: combinational and finite state machines (FSMs) Ø Functionality must be embedded onto the FPGA Ø comprehensive architecture emulation if read-protected RAM and ROM can also be embedded in the FPGA An Altera Cyclone III FPGA was the device selected ESI 2015 27

Motor controller with FPGA: first test setup PLDs read-out succeeded: fuse map disassembled VHDL Peripheral controller: open core embedded Discrete u. P (external) RAM/ROM modeled (synchronous) LVT family buffers selected for interfacing the 5 V side • Test OK • PCB ongoing! Buffers Cyclone III FPGA (Altera Demo Kit) MC 68 SEC 000 ESI 2015 28

Thanks for your attention! Dr. Ignacio Molina European Southern Observatory ESI 2015