FPGAs and VHDL Lecture L 12 1 FPGAs

FPGAs and VHDL Lecture L 12. 1

FPGAs and VHDL • Field Programmable Gate Arrays (FPGAs) • VHDL – 2 x 1 MUX – 4 x 1 MUX – An Adder – Binary-to-BCD Converter – A Register – Fibonacci Sequence Generator

Block diagram of Xilinx Spartan IIE FPGA

Each Spartan IIE CLB contains two of these CLB slices

Look Up Tables • Combinatorial Logic is stored in 16 x 1 SRAM Look Up Tables (LUTs) in a CLB Look Up Table 4 -bit address • Example: Combinatorial Logic A B C D A B Z C D w Capacity is limited by number of inputs, not complexity w Choose to use each function generator as 4 input logic (LUT) or as high speed sync. dual port RAM WE G 4 G 3 G 2 G 1 G Func. Gen. 0 0 0 0 0 1 1 0 0 0 1 0 1 Z 0 0 0 1 1 1 . . . 1 1 1 1 0 0 1 1 0 1 0 0 0 1 4 2(2 ) = 64 K !

Introduction to VHDL • VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language • IEEE standard specification language (IEEE 1076 -1993) for describing digital hardware used by industry worldwide • VHDL enables hardware modeling from the gate level to the system level

Combinational Circuit Example 8 -line 2 -to-1 Multiplexer a(7: 0) b(7: 0) 8 -line 2 x 1 MUX sel y(7: 0) sel 0 1 y a b

An 8 -line 2 x 1 MUX a(7: 0) 8 -line 2 x 1 MUX library IEEE; use IEEE. std_logic_1164. all; b(7: 0) entity mux 2 is sel port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux 2; y(7: 0)

Entity Each entity must begin with these library and use statements library IEEE; use IEEE. std_logic_1164. all; entity mux 2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux 2; port statement defines inputs and outputs

Entity Mode: in or out library IEEE; use IEEE. std_logic_1164. all; entity mux 2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux 2; Data type: STD_LOGIC, STD_LOGIC_VECTOR(7 downto 0);

Architecture architecture mux 2_arch of mux 2 is begin mux 2_1: process(a, b, sel) begin a(7: 0) if sel = '0' then y <= a; b(7: 0) else y <= b; end if; end process mux 2_1; end mux 2_arch; 8 -line 2 x 1 MUX y(7: 0) sel Note: <= is signal assignment

Architecture entity name process sensitivity architecture mux 2_arch of mux 2 is list begin mux 2_1: process(a, b, sel) begin Sequential statements if sel = '0' then (if…then…else) must y <= a; be in a process else y <= b; end if; end process mux 2_1; end mux 2_arch; Note begin…end in architecture Note begin…end in process

An 8 -line 4 x 1 multiplexer a(7: 0) b(7: 0) c(7: 0) d(7: 0) 8 -line 4 x 1 MUX sel(1: 0) y(7: 0) Sel “ 00” “ 01” “ 10” “ 11” y a b c d

An 8 -line 4 x 1 multiplexer library IEEE; use IEEE. std_logic_1164. all; entity mux 4 is port ( a: in STD_LOGIC_VECTOR (7 downto 0); b: in STD_LOGIC_VECTOR (7 downto 0); c: in STD_LOGIC_VECTOR (7 downto 0); d: in STD_LOGIC_VECTOR (7 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (7 downto 0) ); end mux 4;

Example of case statement architecture mux 4_arch of mux 4 is begin Note implies operator => process (sel, a, b, c, d) begin case sel is Sel y when "00" => y <= a; “ 00” a when "01" => y <= b; “ 01” b when "10" => y <= c; when others => y <= d; “ 10” c end case; “ 11” d end process; end mux 4_arch; Must include ALL posibilities in case statement

An Adder -- Title: adder library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_unsigned. all; entity adder is generic(width: positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end adder; architecture adder_arch of adder is Note: + sign synthesizes begin add 1: process(a, b) an n-bit full adder! begin y <= a + b; end process add 1; end adder_arch;

Binary-to-BCD Converter

-- Title: Binary-to-BCD Converter library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_unsigned. all; entity binbcd is port ( B: in STD_LOGIC_VECTOR (7 downto 0); P: out STD_LOGIC_VECTOR (9 downto 0) ); end binbcd;

rchitecture binbcd_arch of binbcd is egin bcd 1: process(B) variable z: STD_LOGIC_VECTOR (17 downto 0); begin for i in 0 to 17 loop z(i) : = '0'; end loop; z(10 downto 3) : = B; for i in 0 to 4 loop if z(11 downto 8) > 4 then z(11 downto 8) : = z(11 downto 8) + 3; end if; if z(15 downto 12) > 4 then z(15 downto 12) : = z(15 downto 12) + 3; end if; z(17 downto 1) : = z(16 downto 0); end loop; P <= z(17 downto 8); end process bcd 1; nd binbcd_arch;

A Register -- A width-bit register library IEEE; use IEEE. std_logic_1164. all; entity reg is generic(width: positive); port ( d: in STD_LOGIC_VECTOR (width-1 downto 0); load: in STD_LOGIC; clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (width-1 downto 0) ); end reg;

Register architecture reg_arch of reg is begin process(clk, clr) begin if clr = '1' then for i in width-1 downto 0 loop q(i) <= '0'; end loop; elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; Infers a flip-flop for end process; outputs (q) end reg_arch; all

Fibonacci Sequence -- Title: Fibonacci Sequence library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE. std_logic_unsigned. all; entity fib is port( clr : in std_logic; clk : in std_logic; P : out std_logic_vector(9 downto 0) ); end fib; P

architecture fib_arch of fib is Declare components component adder generic( width : POSITIVE); port( a : in std_logic_vector((width-1) downto 0); b : in std_logic_vector((width-1) downto 0); y : out std_logic_vector((width-1) downto 0)); end component; component reg generic( width : POSITIVE); port( d : in std_logic_vector((width-1) downto 0); load : in std_logic; clr : in std_logic; set : in std_logic; clk : in std_logic; q : out std_logic_vector((width-1) downto 0)); end component;

component binbcd port( B : in std_logic_vector(7 downto 0); P : out std_logic_vector(9 downto 0)); end component; signal r, s, t: std_logic_vector(7 downto 0); signal one, zero: std_logic; constant bus_width: positive : = 8;

begin one <= '1'; zero <= '0'; U 1: adder generic map(width => bus_width) port map (a => t, b => r, y => s); R 1: reg generic map(width => bus_width) port map (d => r, load =>one, clr => zero, set => clr, clk =>clk, q => t); W: reg generic map(width => bus_width) port map (d => s, load => one, clr => clr, set => zero, clk =>clk, q => r); U 2: binbcd port map (B => r, P => P); end fib_arch; Wire up the circuit

Fibonacci Sequence Works!