BitLine Leakage Cancellation Design and Test Automation Sudhanshu

Bit-Line Leakage Cancellation: Design and Test Automation Sudhanshu Khanna April 22, 2010 1

Deliverables l Bit-Line Leakage Cancellation l l l Schematic Layout On-Chip High Speed Testing l Memory BIST April 22, 2010 BOTTOM – UP DESIGN TOP – DOWN DESIGN 2

Goals: L 1 Cache design l Achieve High Density l l Achieve High Speed l l How: More Bit-Cells, Less Periphery How: Lower Read Time Challenges (Scaling issues) l l l Lower VDD Lower Iread Higher Ileakage April 22, 2010 3

Why is Bit-Line Leakage an Issue l Only solution: Reduce # cells on a bit-line => Lower Density l Bit-line leakage is Data-dependent April 22, 2010 4

Why is Bit-Line Leakage an Issue l SA differential = V(BL) – V(BLB) l If BL leaks, differential lowers l More time needed to generate same differential => Lower Speed April 22, 2010 5

High Speed Testing Issues Signal Analyzer TESTER ~ 100 MHz ~ 20 MHz 1 GHz Inverter OUTPUT PAD ~ 200 MHz April 22, 2010 You can make a FAST inverter, but you cant see it work 6

Memory BIST High Speed Clock F S M Start External Tester (Slow Testing) Data generator Address generator Control generator Done BIST mode Memory Fail

M-BIST Design Flow Algorithm Behavioral Verilog: NC-Verilog Structural Verilog: RTL Compiler Place and Route: Encounter Integration with Custom Memory: Virtuoso April 22, 2010 8

Top-Down Flow Issues Faced l RTL Complier l l l Encounter l l Assign Statements Unused Nets connect to VDD, VSS l Inputs of standard blocks e. g. Carry-In of Adder l Unused bus signals: e. g. Z[4] of a bus Z[11: 0] < > vs [] Virtuoso: l Global Signals April 22, 2010 9

Thanks for your time ! April 22, 2010 10