TSSETS 10 Fault Models Fault Simulation and Test

  • Slides: 27
Download presentation
TSS@ETS 10 Fault Models, Fault Simulation and Test Generation Vishwani D. Agrawal Department of

TSS@ETS 10 Fault Models, Fault Simulation and Test Generation Vishwani D. Agrawal Department of ECE, Auburn University Auburn, AL 36849, USA www. ece. auburn. edu/~vagrawal@eng. auburn. edu Prague, May 22, 2010, 2: 30 -6: 30 PM © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 1

Combinational ATPG n n n © 2001 Agrawal, Bushnell ATPG problem Example Algorithms Multi-valued

Combinational ATPG n n n © 2001 Agrawal, Bushnell ATPG problem Example Algorithms Multi-valued algebra D-algorithm Podem Other algorithms ATPG system Summary Problems to solve May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 2

ATPG Problem n ATPG: Automatic test pattern generation Given n n A circuit (usually

ATPG Problem n ATPG: Automatic test pattern generation Given n n A circuit (usually at gate-level) A fault model (usually stuck-at type) Find n n n A set of input vectors to detect all modeled faults. Core solution: Find a test vector for a given fault. Combine the “core solution” with a fault simulator into an ATPG system. © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 3

What is a Test? Fault activation Fault effect Primary inputs (PI) X 1 0

What is a Test? Fault activation Fault effect Primary inputs (PI) X 1 0 0 1 X X Combinational circuit 1/0 Stuck-at-0 fault © 2001 Agrawal, Bushnell 1/0 Primary outputs (PO) Path sensitization May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 4

Multiple-Valued Algebras Symbol Fault-free Faulty Alternative Representation circuit Circuit D D 0 1 X

Multiple-Valued Algebras Symbol Fault-free Faulty Alternative Representation circuit Circuit D D 0 1 X G 0 G 1 F 0 F 1 © 2001 Agrawal, Bushnell 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 1 0 0 1 X X X 0 1 Roth’s Algebra Muth’s Additions May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 5

An ATPG Example 1 Fault activation 2 Path sensitization 3 Line justification 1 D

An ATPG Example 1 Fault activation 2 Path sensitization 3 Line justification 1 D © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 6

ATPG Example (Cont. ) 1 Fault activation 2 Path sensitization 3 Line justification D

ATPG Example (Cont. ) 1 Fault activation 2 Path sensitization 3 Line justification D D 1 D D © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 7

ATPG Example (Cont. ) 1 Fault activation 2 Path sensitization 3 Line justification 1

ATPG Example (Cont. ) 1 Fault activation 2 Path sensitization 3 Line justification 1 D D 1 1 D Conflict 0 D 1 1 1 © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 8

ATPG Example (Cont. ) Backtrack 1 Fault activation 2 Path sensitization 3 Line justification

ATPG Example (Cont. ) Backtrack 1 Fault activation 2 Path sensitization 3 Line justification 0 0 1 D D D 1 Test found © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 9

D-Algorithm (Roth 1967) n n n Use D-algebra Activate fault n Place a D

D-Algorithm (Roth 1967) n n n Use D-algebra Activate fault n Place a D or D at fault site n Justify all signals Repeatedly propagate D-chain toward POs through a gate n Justify all signals Backtrack if n A conflict occurs, or n All D-chains die Stop when n D or D at a PO, i. e. , test found, or n Search exhausted, no test possible © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 10

Example: Fault A sa 0 n 1 Step 1 – Fault activation – Set

Example: Fault A sa 0 n 1 Step 1 – Fault activation – Set A = 1 D D Gates with unspecified output and a D at input: D-frontier = {e, h} © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 11

Example Continued n Step 2 – D-Drive – Set f = 0 0 1

Example Continued n Step 2 – D-Drive – Set f = 0 0 1 D © 2001 Agrawal, Bushnell D D May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 12

Example Continued n Step 3 – D-Drive – Set k = 1 1 D

Example Continued n Step 3 – D-Drive – Set k = 1 1 D 0 1 D © 2001 Agrawal, Bushnell D D May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 13

Example Continued n Step 4 – Consistency – Set g = 1 1 1

Example Continued n Step 4 – Consistency – Set g = 1 1 1 D 0 1 D © 2001 Agrawal, Bushnell D D May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 14

Example Continued n Step 5 – Consistency – f = 0 Already set 1

Example Continued n Step 5 – Consistency – f = 0 Already set 1 1 D 0 1 D © 2001 Agrawal, Bushnell D D May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 15

Example Continued n Step 6 – Consistency – Set c = 0, Set e

Example Continued n Step 6 – Consistency – Set c = 0, Set e = 0 1 1 D © 2001 Agrawal, Bushnell 0 D D May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 16

Example: Test Found n n Step 7 – Consistency – Set B = 0

Example: Test Found n n Step 7 – Consistency – Set B = 0 Test: A = 1, B = 0, C = 0, D = X X 1 0 0 1 1 D © 2001 Agrawal, Bushnell 0 D D May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 17

Podem (Goel, 1981) n n Podem: Path oriented decision making Step 1: Define an

Podem (Goel, 1981) n n Podem: Path oriented decision making Step 1: Define an objective (fault activation, D-drive, or line justification) Step 2: Backtrace from site of objective to PIs (use testability measures guidance) to determine a value for a PI Step 3: Simulate logic with new PI value n n If objective not accomplished but is possible, then continue backtrace to another PI (step 2) If objective accomplished and test not found, then define new objective (step 1) If objective becomes impossible, try alternative backtrace (step 2) Use X-PATH-CHECK to test whether D-frontier still there – a path of X’s from a D-frontier to a PO must exist. © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 18

Podem Example 3. Logic simulation for A=0 2. Backtrace “A=0” 1. Objective “ 0”

Podem Example 3. Logic simulation for A=0 2. Backtrace “A=0” 1. Objective “ 0” 0 S-a-1 (9, 2) 4. Objective possible but not accomplished © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 19

Podem Example (Cont. ) 6. Logic simulation for A=0, B=0 5. Backtrace “B=0” 1.

Podem Example (Cont. ) 6. Logic simulation for A=0, B=0 5. Backtrace “B=0” 1. Objective “ 0” 0 0 0 S-a-1 0 (9, 2) 7. Objective possible but not accomplished © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 20

Podem Example (Cont. ) 9. Logic simulation for E=0 8. Backtrace “E=0” 1. Objective

Podem Example (Cont. ) 9. Logic simulation for E=0 8. Backtrace “E=0” 1. Objective “ 0” 0 0 0 S-a-1 0 (9, 2) 10. Objective possible but not accomplished © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 21

Podem Example (Cont. ) 12. Logic simulation for D=0 1. Objective “ 0” 0

Podem Example (Cont. ) 12. Logic simulation for D=0 1. Objective “ 0” 0 0 0 S-a-1 0 (9, 2) 0 0 13. Objective accomplished © 2001 Agrawal, Bushnell 11. Backtrace “D=0” May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 22

An ATPG System Random pattern generator Fault simulator yes Save patterns yes Fault coverage

An ATPG System Random pattern generator Fault simulator yes Save patterns yes Fault coverage improved? no Random patterns effective? Deterministic ATPG (D-alg. no or Podem) Stop if fault coverage goal achieved © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 23

Summary n n Most combinational ATPG algorithms use D-algebra. D-Algorithm is a complete algorithm:

Summary n n Most combinational ATPG algorithms use D-algebra. D-Algorithm is a complete algorithm: n Finds a test, or n Determines the fault to be redundant n Complexity is exponential in circuit size Podem is also a complete algorithm: n Works on primary inputs – search space is smaller than that of D-algorithm n Exponential complexity, but several orders faster than Dalgorithm More efficient algorithms available – FAN, Socrates, etc. n See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 7. © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 24

Problems to Solve n n For the circuit shown above derive a test for

Problems to Solve n n For the circuit shown above derive a test for the stuck -at-1 fault at the output of the AND gate. Using the parallel fault simulation algorithm, determine which of the four primary input faults are detectable by the test derived above. © 2001 Agrawal, Bushnell May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 25

Solution ■ A test for the stuck-at-1 fault shown in the diagram is 00.

Solution ■ A test for the stuck-at-1 fault shown in the diagram is 00. 0 0 © 2001 Agrawal, Bushnell 0 D s-a-1 D May 22, 2010, Agrawal: Lecture 4 Combinational ATPG 26

Solution Cont. ■ Parallel fault simulation of four PI faults is illustrated below. Fault

Solution Cont. ■ Parallel fault simulation of four PI faults is illustrated below. Fault PI 2 s-a-1 is detected by the 00 test input. 00100 00001 PI 2=0 No fault PI 1 s-a-0 PI 1 s-a-1 PI 2 s-a-0 PI 2 s-a-1 00001 © 2001 Agrawal, Bushnell 00001 May 22, 2010, Agrawal: Lecture 4 Combinational ATPG PI 2 s-a-1 detected PI 1=0 27

TSSETS 10 Fault Models Fault Simulation and TestTSSETS 10 Fault Models Fault Simulation and Test
TSSETS 10 Fault Models Fault Simulation and TestTSSETS 10 Fault Models Fault Simulation and Test
TSSETS 10 Fault Models Fault Simulation and TestTSSETS 10 Fault Models Fault Simulation and Test
TSSETS 10 Fault Models Fault Simulation and TestTSSETS 10 Fault Models Fault Simulation and Test
TSSETS 10 Fault Models Fault Simulation and TestTSSETS 10 Fault Models Fault Simulation and Test
TSSETS 10 Fault Models Fault Simulation and TestTSSETS 10 Fault Models Fault Simulation and Test
1 Simulation Simulation Simulation Computer Model Simulation Simulation1 Simulation Simulation Simulation Computer Model Simulation Simulation
TSSETS 10 Logic Simulation Vishwani D Agrawal DepartmentTSSETS 10 Logic Simulation Vishwani D Agrawal Department
Active Fault An active fault is a faultActive Fault An active fault is a fault
Normal Fault Normal Fault A normal fault actsNormal Fault Normal Fault A normal fault acts
WITNESS Simulation simulation simulation simulation part Seat ArrivalWITNESS Simulation simulation simulation simulation part Seat Arrival
Fault Modeling Simulation and Diagnosis Fault Modeling FaultsFault Modeling Simulation and Diagnosis Fault Modeling Faults
MODELS AND TECHNOLOGICAL DESIGN MODELS MODELS Models helpMODELS AND TECHNOLOGICAL DESIGN MODELS MODELS Models help
Diagnostic Test Generation and Fault Simulation Algorithms forDiagnostic Test Generation and Fault Simulation Algorithms for
Diagnostic Test Pattern Generation and Fault Simulation forDiagnostic Test Pattern Generation and Fault Simulation for
Experimental Probability and Simulation Simulation A simulation imitatesExperimental Probability and Simulation Simulation A simulation imitates
Experimental Probability and Simulation Simulation A simulation imitatesExperimental Probability and Simulation Simulation A simulation imitates
Penetration Test Pen Test Penetration Test Pen TestPenetration Test Pen Test Penetration Test Pen Test
Test Method Test Company Test Number Standard TestTest Method Test Company Test Number Standard Test
Test Development Test conceptualization Test construction Test tryoutTest Development Test conceptualization Test construction Test tryout
Test Test test 012 multiple class Test intTest Test test 012 multiple class Test int
Test Test test 012 multiple class Test intTest Test test 012 multiple class Test int
0 test 1242 test 1673 test 179 test0 test 1242 test 1673 test 179 test
Populous Simulation options 20041028001 Simulation options Simulation dataPopulous Simulation options 20041028001 Simulation options Simulation data