TLU plans 16092020 D Esperante Velo upgrade meeting

TLU plans 16/09/2020 D. Esperante, Velo upgrade meeting 1

Motivation · Have a compact trigger logic unit in one board instead of tens of VME modules and lemo cables dangling around. · Easy configuration of trigger logic remotely with added functionalities such as test readout elements (Time. Pix + DUT) without beam (ie auto trigger). · Make the logic a bit generic such it can be attached to LHC like read-out systems. · Implement a TDC that provides timing information. 16/09/2020 D. Esperante, Velo upgrade meeting 2

General scheme (1) Control PC Ethernet Control data Readout PC GBE TLU data Embedded system based on Altera Stratix II FPGA development board 16/09/2020 External input trigger signals from NIM logic External veto signals Output trigger signals to telescope + DUT D. Esperante, Velo upgrade meeting 3

General scheme (2) Ethernet Control data via webservices GBE TDC data (to be defined) DMA NIOS II processor SDRAM (control software) 16/09/2020 SRAM (TDC data) External input trigger signals DMA Veto/enable signals Coincidence signal sampling + TDC + trigger generator D. Esperante, Velo upgrade meeting Output trigger signals 4

Signaling example Spill signal Shutter signal RO time Beetle trigger signal 40 MHz clock 16/09/2020 D. Esperante, Velo upgrade meeting 5

GPP: General Purpose Pulser Coincidences Synch trigger Enable signal Start deadtime Pulse output Burst length Dead time General purpose pulser (GPP) Programmable features: - Startup dead time. - Pulse length. - Inter-pulse dead-time. - Max pulse count. - Output delay in clock cycles. - With or without repetition. - Programmable multiplexor input to select several sources of enable/veto. - Programmable multiplexor input to select several sources of force cero output. - Force pull-down. 16/09/2020 D. Esperante, Velo upgrade meeting 6

GPP 2 · Using several GPPs with multiplexor at the enable/veto and “force-pull down” inputs we can implement the different output signals: · Spill signal: · Long burst length. · With repetition. · Timepix shutter signal: · Burst length modulated by external “force ‘ 0’ output”. · Dead time = timepix readout time. · Beetle trigger signal: · Burst length = ‘ 1’. · Dead time = ‘ 0’. · Max counter. · Veto/enable multiplexors: · The Spill signal enables the “Timepix shutter” and the “Beetle trigger” signals. · The “Beetle trigger” max counter forces the pull-down of the “Timepix shutter”. 16/09/2020 D. Esperante, Velo upgrade meeting 7

Internal scheme (1) Coincidence signal sampling + TDC + trigger generator CLK 160 CLK 80 CLK 40 TDC 1 EN CLK 40 Coincidence RST CLK 40 General purpose pulser (GPP) EN CLK 40 Internal pulse generator 16/09/2020 Max-cnt Shutter Signal detection and synchronization External veto/enable CLK 20 Force pull-down RST Force pull-down General purpose pulser (GPP) D. Esperante, Velo upgrade meeting Max-cnt 25 ns trigger 8

The TDC (‘s) TDC Features: - Implementation based on multiphase clock based on multiple of 40 MHz (240 MHz). Resolution around 1 ns. See “High-Precision TDC in an FPGA using 192 -MHz Quadrature Clock”, Mark D. Fries, John J. Williams, Nuclear Science Symposium Conference Record, 2002 IEEE. 10/12/2002; 1: 580584 vol. 1. - 32 -40 bits time counter. - Some extra bits with extra status info. To be defined. - The scheme also defines the signal synchronization circuitry. 16/09/2020 D. Esperante, Velo upgrade meeting 9

16/09/2020 D. Esperante, Velo upgrade meeting 10

Time stamping of output signals · It may be helpful to record the time when a transition in any of the output signals ocurred. Two options: · A TDC per output signal. Too heavy. · Have a clock counter and use it as time stamp. Scatter-gather DMA CLK 40 TDC CLK 40 Time stamper Shutter 16/09/2020 Trigger D. Esperante, Velo upgrade meeting 11

Other technical issues · In this first design make something simple that works: · All clocks synchronous. · Will not use fancy improvements in the logic which would increase the data Tx rate. · Later improvements: · Think about an architecture that permits the TDC and the pulsers work in different clock domains so an external input clock could be used to generate the trigger signal while keeping the TDC untouched. · Zero-suppression… 16/09/2020 D. Esperante, Velo upgrade meeting 12

Other technical issues · NIM voltage levels compatibility: · Use LVPECL or build a small adapter board. · In the future, maybe we could build a plug-in board with the discriminators and coincidence units. · Output data format: · To be defined. · Software development needed: · Firmware for the embedded system. · TLU reader: the Rx software at the readout PC. · TLU controller: webservices based control (html page). 16/09/2020 D. Esperante, Velo upgrade meeting 13

Status · Embedded system with the NIOS II processor, SRAM, SDRAM, Ethernet link working. GBE not implemented yet. · Writing the VHDL for the pulser and performing the functional simulations. · Still quite a lot to do… · I’ll be away for some weeks… 16/09/2020 D. Esperante, Velo upgrade meeting 14