STARLight Sensor Signal Processing Ryan Miller STARLight Electrical

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STARLight Sensor Signal Processing Ryan Miller STARLight Electrical Engineer (734) 763 -5373 rpmiller@umich. edu

STARLight Sensor Signal Processing Ryan Miller STARLight Electrical Engineer (734) 763 -5373 rpmiller@umich. edu STARLight PDR 3 Oct ‘ 01 H. 1 Miller

STARLight • • Overview Sensor Requirements Signal Processing Chain Overview Sampling Digital Signal Processing

STARLight • • Overview Sensor Requirements Signal Processing Chain Overview Sampling Digital Signal Processing Data Formatting and Rates Hardware Overview Power Summary STARLight PDR 3 Oct ‘ 01 H. 2 Miller

STARLight Sensor Requirements • Sample 10 1. 413 GHz, band-limited signals – < 20

STARLight Sensor Requirements • Sample 10 1. 413 GHz, band-limited signals – < 20 ps sample to sample jitter – < 6. 7 ns channel to channel sample skew – 3 -bit digitization • Digitally filter the data to ease requirements on analog filter • Recover the Inphase and Quadrature components of each of the 10 signals • Calculate digitization statistics for each ADC • Allow gain/offset adjustment for each ADC to optimize 3 bit conversion • Monitor critical receiver temperatures • Provide thermal control electronics STARLight PDR 3 Oct ‘ 01 H. 3 Miller

STARLight PDR 3 Oct ‘ 01 System Block Diagram H. 4 Miller

STARLight PDR 3 Oct ‘ 01 System Block Diagram H. 4 Miller

STARLight PDR 3 Oct ‘ 01 Signal Processing Chain H. 5 Miller

STARLight PDR 3 Oct ‘ 01 Signal Processing Chain H. 5 Miller

STARLight Sampling • Minimum sample rate (Fs) is 2 times bandwidth • Bandwidth must

STARLight Sampling • Minimum sample rate (Fs) is 2 times bandwidth • Bandwidth must include the analog Pre-Sample Filter ‘skirts’ • Sample rate must be selected so that sampled data is aliased to Fs/4 for quadrature demodulation • Since the Band Definition Filter is digital, would like to relax the analog Pre-Sample Filter specification – Wider Bandwidth – Gentler Roll-off/Fewer Poles STARLight PDR 3 Oct ‘ 01 H. 6 Miller

STARLight PDR 3 Oct ‘ 01 Sample Rate Calculations H. 7 Miller

STARLight PDR 3 Oct ‘ 01 Sample Rate Calculations H. 7 Miller

STARLight Possible Sample Rates • Nyquist Sample Rate = 72 MHz • Fs/4 =

STARLight Possible Sample Rates • Nyquist Sample Rate = 72 MHz • Fs/4 = F 0/(2 M-1) • Minimum sample rate = 73. 4 MHz – Fs/4 = 18. 35 MHz – Pre-Sample Filter BW limited to 36. 7 MHz • Desired sample rate = 102. 8 MHz – Fs/4 = 25. 7 MHz – Pre-Sample Filter BW can be 51 MHz – After digital filtering and Quadrature Demod, can decimate by a factor of 2 STARLight PDR 3 Oct ‘ 01 H. 8 Miller

Results of Sampling at 102. 8 MHz STARLight PDR 3 Oct ‘ 01 H.

Results of Sampling at 102. 8 MHz STARLight PDR 3 Oct ‘ 01 H. 9 Miller

STARLight The Next Step… • Digital Filter before Quadrature Demodulation – PRO: Only need

STARLight The Next Step… • Digital Filter before Quadrature Demodulation – PRO: Only need 10 filters – CON: Must operate at 100+ MHz Filter must be band-pass • Quadrature Demodulation before Digital Filter – PRO: Reduces data rate by factor of 2 Digital Filter becomes low-pass Quadrature Demod includes FIRs – might be able to combine – CON: Need 20 digital filters STARLight PDR 3 Oct ‘ 01 H. 10 Miller

Digital Filtering then Quad Demod. STARLight • Reduced hardware complexity – Fewer filters =

Digital Filtering then Quad Demod. STARLight • Reduced hardware complexity – Fewer filters = less hardware – Band-pass FIR may require more stages, but not twice as many • Speed – – – Depends on FPGA specifications and implementation I/O is spec’d at 300 MHz Implementation is flexible, Transposed form FIR relies on fast adders Xilnx FPGAs have built in adder support 64 -bit ADD spec’d at 150 MHz STARLight PDR 3 Oct ‘ 01 H. 11 Miller

STARLight Digital Filtering First • Define the final signal bandwidth using a digital filter

STARLight Digital Filtering First • Define the final signal bandwidth using a digital filter – Allows identical filters to be used on all channels – Allows some relaxation of analog Pre-Sample Filter and minimizes channel to channel matching requirements • Requires at least 30 stage bandpass FIR • For 30 Stage, 16 -bit (approx. ): – 30*16+30*3 = 570 Registers/Filter – 10 Filters require 5700 registers – Xilinx XCV 600 has over 15, 000 registers STARLight PDR 3 Oct ‘ 01 H. 12 Miller

STARLight Transposed Form FIR Filter • Samples go to all taps simultaneously • Tap

STARLight Transposed Form FIR Filter • Samples go to all taps simultaneously • Tap coefficient multiplies implemented with lookups • All adders are 2 -input: Reduces cascading, increases speed STARLight PDR 3 Oct ‘ 01 H. 13 Miller

Matlab Designed Quantized FIR STARLight • Used Matlab Filter Design Toolbox • Designed for

Matlab Designed Quantized FIR STARLight • Used Matlab Filter Design Toolbox • Designed for quantized 10 -bit coefficients • Sample filter design with 31 taps • Filter is symmetric • Filter is linear phase • Can save hardware since half the coefficients are zero STARLight PDR 3 Oct ‘ 01 H. 14 Miller

STARLight PDR 3 Oct ‘ 01 Quantized Filter Response H. 15 Miller

STARLight PDR 3 Oct ‘ 01 Quantized Filter Response H. 15 Miller

STARLight • • Quadrature Demodulation Mix digitized signal with sine and cosine (0, 1,

STARLight • • Quadrature Demodulation Mix digitized signal with sine and cosine (0, 1, 0, -1, …) Filter the results Produces the Inphase and Quadrature components Each component is at half the sample rate STARLight PDR 3 Oct ‘ 01 H. 16 Miller

I & Q Recovery Implementation STARLight • The mixing operation is combined with the

I & Q Recovery Implementation STARLight • The mixing operation is combined with the FIR operation and replaced with a multiplexor • The Inphase channel is simply delayed • The Quadrature channel is filtered with a simplified Hilbert Transform FIR (90° phase shift) STARLight PDR 3 Oct ‘ 01 H. 17 Miller

STARLight Sampling Summary • Resulting 12 MHz bandwidth of I and Q channels requires

STARLight Sampling Summary • Resulting 12 MHz bandwidth of I and Q channels requires only 24 MHz Sample rate per channel (25. 7 MHz) STARLight PDR 3 Oct ‘ 01 H. 18 Miller

STARLight Other Sensor Functions • Channel Totalizing Counters – 7 counters for each channel

STARLight Other Sensor Functions • Channel Totalizing Counters – 7 counters for each channel – Count occurrences of each binary value over the integration period • Housekeeping Data Collection – Up to 6 receiver temperature monitors • Thermal Control – PWM plus drive electronics for heater in each receiver STARLight PDR 3 Oct ‘ 01 H. 19 Miller

STARLight Sensor Data Rates • 73. 4 MHz sampling – Raw bit rate: 10

STARLight Sensor Data Rates • 73. 4 MHz sampling – Raw bit rate: 10 channels *3 bits * 73. 4 MHz = 2. 2 Gbps – After I/Q Demod: 20 channels *3 bits * 36. 7 MHz = 2. 2 Gbps • 102. 8 MHz sampling – Raw bit rate: 10 channels *3 bits * 102. 8 MHz = 3. 1 Gbps – After I/Q Demod: 20 channels *3 bits * 25. 7 MHz = 1. 5 Gbps • Totalizer Output (one second integration) – 10 channels * 7 bins/channel * 29 bits per bin = 2030 bits/sec • Temperature Data – 10 channels * 6 temps/channel * 16 bits/temp = 960 bits/sec STARLight PDR 3 Oct ‘ 01 H. 20 Miller

STARLight PDR 3 Oct ‘ 01 Hardware Overview H. 21 Miller

STARLight PDR 3 Oct ‘ 01 Hardware Overview H. 21 Miller

STARLight PDR 3 Oct ‘ 01 Sensor Data Acquisition H. 22 Miller

STARLight PDR 3 Oct ‘ 01 Sensor Data Acquisition H. 22 Miller

STARLight PDR 3 Oct ‘ 01 A/D Converter Comparison H. 23 Miller

STARLight PDR 3 Oct ‘ 01 A/D Converter Comparison H. 23 Miller

STARLight SPT 7610 A/D Selected • Power – Lowest power of the 3 available

STARLight SPT 7610 A/D Selected • Power – Lowest power of the 3 available • Package – Flat-package – Maxim only available in Ball-Grid Array Package • Temperature Range – Available in Industrial Temp. Range (-40 to +85 C) – Maxim only available in Commercial Temp. Range (0 to 70 C) • Availability – Parts in-house – Atmel: $888. 00 ea, Minimum order of 4, 16 -week lead time STARLight PDR 3 Oct ‘ 01 H. 24 Miller

STARLight PDR 3 Oct ‘ 01 Sensor Control Board H. 25 Miller

STARLight PDR 3 Oct ‘ 01 Sensor Control Board H. 25 Miller

Sensor Housekeeping Data Acquisition STARLight • • Low-speed 16 -bit A/D Converter Interface electronics

Sensor Housekeeping Data Acquisition STARLight • • Low-speed 16 -bit A/D Converter Interface electronics for up to 6 thermistors Reference electronics to improve accuracy Low-speed data will be time-tagged and read on demand by the Control Computer through the Status and Control Interface STARLight PDR 3 Oct ‘ 01 H. 26 Miller

STARLight Sensor Power Summary • Sensor Data Acquisition Board (x 10 boards, not including

STARLight Sensor Power Summary • Sensor Data Acquisition Board (x 10 boards, not including Receiver) – 7. 0 Watts Maximum – 5. 4 Watts Typical • Sensor Control Board: – 6. 0 Watts Maximum STARLight PDR 3 Oct ‘ 01 H. 27 Miller

STARLight FPGA Tradeoffs • Altera – PRO: In-house experience High-speec, high-density devices – CON:

STARLight FPGA Tradeoffs • Altera – PRO: In-house experience High-speec, high-density devices – CON: No extended temperature range devices Large devices in non-BGA packages have limited I/O capabilities More expensive tools • Xilinx Selected – PRO: High-speed, high-density devices Devices support many I/O standards including LVDS and LVPECL Available in extended temperature range versions Less expensive tools (although Model. Sim simulator is ‘extra’) – CON: ? STARLight PDR 3 Oct ‘ 01 H. 28 Miller

STARLight Design Status • Sensor Data Acquisition Board: – – Prototype and Flight boards

STARLight Design Status • Sensor Data Acquisition Board: – – Prototype and Flight boards are identical Schematic 75% complete Most components ordered and received FPGA Design 10% complete • Sensor Control Board: – – Prototype and Flight boards are identical Schematic 25% complete Most components ordered and received FPGA Design 10% complete • Development Tools: – Schematic capture: Mc. Cad – FPGA Development: Xilinx ISE & Model. Sim – Analysis: Matlab, Simulink STARLight PDR 3 Oct ‘ 01 H. 29 Miller

STARLight PDR 3 Oct ‘ 01 Schedule H. 30 Miller

STARLight PDR 3 Oct ‘ 01 Schedule H. 30 Miller