Readout Controller ROC Specifications and Status Report July

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Readout Controller (ROC) Specifications and Status Report July 10 Traian Tulbure

Readout Controller (ROC) Specifications and Status Report July 10 Traian Tulbure

Block diagram of the Readout Controller

Block diagram of the Readout Controller

VMM Capture Consists of the following blocks: • DES • comma. Align • VMM

VMM Capture Consists of the following blocks: • DES • comma. Align • VMM DEC • ASSEMBL • FIFO

DES

DES

COMMA ALIGN

COMMA ALIGN

VMM DEC

VMM DEC

ASSEMBL

ASSEMBL

x. Bar

x. Bar

s. ROC

s. ROC

s. ROC flow diagram

s. ROC flow diagram

VMM Capture simulation • Compare the two log files • Their content should be

VMM Capture simulation • Compare the two log files • Their content should be identical

VMM Capture simulation - issues • Comma. Align loss of alignment when data is

VMM Capture simulation - issues • Comma. Align loss of alignment when data is received after ‘comma’ – Caused by phshift being reset after ‘comma’ is not received: always @(posedge ck_i or negedge reset_ni) . . . if (data_valid_i) begin casex(is. Alligned) . . . default: {found. K, phshift} <= {1'b 0, 4'd 0}; – Solved: default: {found. K, phshift} <= {1'b 0, phshift};

VMM Capture simulation - issues • Hit data considered header because first bit is

VMM Capture simulation - issues • Hit data considered header because first bit is ‘ 0’ – caused by Assembler, first bit was checked regardless of current state always@(posedge clk_160_i or negedge reset_n_i) begin . . . else if(~dec_data_i_del[7] & en) begin is_header <= 'b 1; end – Solved: else if(~dec_data_i_del[7] & en & ring_counter_0001[0]) begin

VMM Capture simulation • After solving the issues , the simulation was run for

VMM Capture simulation • After solving the issues , the simulation was run for 18 hours • Simulation time : 10 s • Number of generated data words: 43, 368, 372 • Contents of the two log files were identical – No data was lost – Data was correctly received

Current ROC status • Design specification is being developed – https: //miv. unitbv. ro/svn/myrepo/atlas/roc/doc/ROC_Specs-unitbv.

Current ROC status • Design specification is being developed – https: //miv. unitbv. ro/svn/myrepo/atlas/roc/doc/ROC_Specs-unitbv. docx • Verilog RTL code available for: – DES, COMMA_ALIGN, VMM DEC, ASSEMBLER, XBAR, SROC • Integration and test of VMM capture block is in progress • Basic test environment exists (VMM DATA GEN/MONITOR) • Next steps: – Integration of all modules at top-level using simple behavioral models for PLL, TTC decode, configuration. – Starting of top-level simulations to determine FIFO sizes and generate memory blocks – Integration of remaining blocks: PLL, TTC decode, I 2 C, E-link – Adding message processing, first version will not have message processing, error conditions are reported via I 2 C configuration block.