EECS 318 CAD Computer Aided Design LECTURE 6

EECS 318 CAD Computer Aided Design LECTURE 6: State machines Instructor: Francis G. Wolff wolff@eecs. cwru. edu Case Western Reserve University This presentation uses powerpoint animation: please viewshow CWRU EECS 318

VHDL Component, Entity, and Architecture for-generate | if generate Component Instance Component Declaration Entity Architecturei Concurrent Boolean Equations Concurrent With-Select-When-Else Other Concurrent Components CWRU EECS 318

VHDL Components Component Declaration [ Optional ] { repeat } COMPONENT component_entity_name [ GENERIC ( { identifier: type [: = initial_value ]; } ) ] [ PORT ( { identifier: mode type; } ) ] END; Add ; only if another identifier Component Instance identifier : component_entity_name [ GENERIC MAP ( identifier { , identifier } ) ] [ PORT MAP ( identifier { , identifier } ) ] ; mode : = IN | OUT | INOUT type : = std_logic | std_logic_vector(n downto 0) | bit CWRU EECS 318

VHDL Concurrent Statements Boolean Equations relation : : = relation LOGIC relation | NOT relation | ( relation ) LOGIC : : = AND | OR | XOR | NAND | NOR | XNOR Example: y <= NOT (a) AND NOT (b) ) Multiplexor case statement WITH select_signal SELECT signal <= signal_value 1 WHEN select_compare 1, • • • WHEN select_comparen; Example: 2 to 1 multiplexor WITH s SELECT y <= a WHEN ‘ 0’, b WHEN OTHERS; CWRU EECS 318

VHDL Concurrent Statements Conditionial signal assignment signal <= signal_value 1 WHEN condition 1 ELSE • • • signal_valuen WHEN conditionn; ELSE signal_valuen+1 Example: Priority Encoder y <= a WHEN s=‘ 0’ ELSE b; CWRU EECS 318

SR Flip-Flop (Latch) R S Q Q R 0 0 1 1 NOR S Qn+1 0 Qn 1 1 0 0 1 U R 0 0 1 1 NAND S Qn+1 0 U 1 1 0 0 1 Qn Q <= R NOR NQ; NQ <= S NOR Q; Q <= R NAND NQ; NQ <= S NAND Q; CWRU EECS 318

SR Flip-Flop (Latch) R 0 0 1 1 NAND S Qn+1 0 U 1 1 0 0 1 Qn R R(t) Q Q(t) Q S S(t) 5 ns Q(t + 5 ns) With Delay Example: R <= ‘ 1’, ‘ 0’ after 10 ns, ‘ 1’ after 30 ns; S <= ‘ 1’; t 0 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns 40 ns R 1 Q U 1 U 0 U 0 0 1 0 1 0 Q U S 1 U 1 1 1 1 CWRU EECS 318

Gated-Clock SR Flip-Flop (Latch Enable) PS Q <= (S NAND LE) NAND NQ; S Q LE Q R CLR NQ <= (R NAND LE) NAND Q; Synchronous: Set and Reset Asynchronous: Preset and Clear Latches require that during the gated-clock the data must also be stable (i. e. S and R) at the same time Suppose each gate was 5 ns: how long does the clock have to be enabled to latch the data? Answer: 15 ns CWRU EECS 318

Rising-Edge Flip-flop CWRU EECS 318

Rising-Edge Flip-flop logic diagram CWRU EECS 318

Synchronous Sequential Circuit CWRU EECS 318

Abstraction: Finite State Machine CWRU EECS 318

FSM Representations CWRU EECS 318

Simple Design Example CWRU EECS 318

State Encoding CWRU EECS 318

Logic Implementations CWRU EECS 318

FSM Observations CWRU EECS 318

Coke Machine Example CWRU EECS 318

Coke Machine State Diagram CWRU EECS 318

Coke Machine Diagram II CWRU EECS 318

Moore Machines CWRU EECS 318

Mealy Machines CWRU EECS 318