Division Discussion D 11 3 Division 1010 1101

Division Discussion D 11. 3

Division 1010 1101 10000111 1101 00111 0000 01111 1101 0000 0101 10 13 135 13 05

Division 8 -bit/4 -bit = 4: 4 1010 1101 10000111 1101 00111 0000 01111 1101 0000 0101 _10000111 numer[8: 0] denom[3: 0] 1101 If denom < numer[7: 4] then overflow (quotient won’t fit in 4 bits) Let T = numer[8: 4] N = numer[3: 0] N 2 = denom[3: 0]

Division 8 -bit/4 -bit = 4: 4 1010 1101 10000111 1101 00111 0000 01111 1101 0000 0101 T N 100001110 1101 shl N 2 for I in 0 to 3 loop shl T & N; if T[4: 0] >= N 2 then T : = T - (0 & N 2); N(0) : = ‘ 1’; end if; end loop;

Division 8 -bit/4 -bit = 4: 4 1010 1101 10000111 1101 00111 0000 01111 1101 0000 0101 T N 100001110 N 2 1101 001111110 1101 011111100 1101 001011010 rem quot sll sub 1 sll

div. vhd Combinational divide -- Title: Division: 8/4 = 4: 4 library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_unsigned. all; entity div is port ( numer: in STD_LOGIC_VECTOR (7 downto 0); denom: in STD_LOGIC_VECTOR (3 downto 0); quot: out STD_LOGIC_VECTOR (3 downto 0); remain: out STD_LOGIC_VECTOR (3 downto 0) ); end div;

div. vhd (cont. ) T architecture div_arch of div is begin div 1: process(numer, denom) 100001110 1101 N 2 variable T, N 2: STD_LOGIC_VECTOR (4 downto 0); variable N: STD_LOGIC_VECTOR (3 downto 0); begin T : = '0' & numer(7 downto 4); N : = numer(3 downto 0); N 2 : = '0' & denom; N

div. vhd (cont. ) for I in 0 to 3 loop T : = T(3 downto 0) & N(3); N : = N(2 downto 0) & '0'; if T >= N 2 then T : = T - N 2; N(0) : = '1'; end if; end loop; quot <= N; remain <= T(3 downto 0); end process div 1; end div_arch; T N 100001110 1101 N 2 shl

div synthesized circuit denom(3: 0) remain(3: 0) quot(3: 0) numer(7: 3) numer(2: 0)

Top-level Design

-- Title: DIV Test DIVtest. vhd library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE. std_logic_unsigned. all; entity DIVtest is port( mclk : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(7 downto 0); BTN : in STD_LOGIC_VECTOR(3 downto 0); LD : out STD_LOGIC_VECTOR(7 downto 0); Ato. G : out STD_LOGIC_VECTOR(6 downto 0); AN : out STD_LOGIC_VECTOR(3 downto 0) ); end DIVtest;

architecture DIVtest_arch of DIVtest is signal r, p: std_logic_vector(15 downto 0); signal clr, clk, cclk: std_logic; signal clkdiv: std_logic_vector(23 downto 0); signal denom: std_logic_vector(3 downto 0); constant bus_width: positive : = 4; begin clr <= BTN(3); -- Divide the master clock (50 Mhz) process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; cclk <= clkdiv(17); -- 190 Hz

p(15 downto 8) <= "0000"; denom <= '0' & BTN(2 downto 0); U 1: divg generic map(width => bus_width) port map (numer => SW, denom => denom, quot => p(3 downto 0), remain =>p(7 downto 4)); U 3: x 7 segb port map (x => p, cclk => cclk, clr => clr, Ato. G => Ato. G, AN => AN); LD <= SW; end DIVtest_arch;

Ato. G(6: 0) x(15: 0) AN(3: 0) x 7 segb

divg. vhd -- Title: Division: 2*width/width = width: width library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_unsigned. all; entity divg is generic(width: positive); port ( numer: in STD_LOGIC_VECTOR (width+width-1 downto 0); denom: in STD_LOGIC_VECTOR (width-1 downto 0); quot: out STD_LOGIC_VECTOR (width-1 downto 0); remain: out STD_LOGIC_VECTOR (width-1 downto 0) ); end divg;

divg. vhd (cont. ) architecture divg_arch of divg is begin div 1: process(numer, denom) variable T, N 2: STD_LOGIC_VECTOR (width downto 0); variable N: STD_LOGIC_VECTOR (width-1 downto 0); begin T : = '0' & numer(width+width-1 downto width); N 2 : = '0' & denom; N : = numer(width-1 downto 0);

begin T : = '0' & numer(width+width-1 downto width); N 2 : = '0' & denom; N : = numer(width-1 downto 0); for j in 0 to width-1 loop T : = T(width-1 downto 0) & N(width-1); N : = N(width-2 downto 0) & '0'; if T >= N 2 then T : = T - N 2; N(0) : = '1'; end if; end loop; quot <= N; remain <= T(width-1 downto 0); end process div 1; end divg_arch;

width = 8