Designing State Machines Discussion D 8 5 Section

Designing State Machines Discussion D 8. 5 Section 13. 9

Sequence Detectors • Mealy and Moore Machines • A Sequence Detector using D Flip-flops • Verilog Program

Canonical Sequential Network s(t+1) next state State Register x(t) Combinational Network clr s(t) present state present input clk present z(t) output

Mealy Machine s(t+1) C 1 x(t) next state State Register clr present input clk s(t) present state z(t) C 2

Moore Machine s(t+1) C 1 x(t) next state State Register clr present input clk z(t) s(t) present state C 2

Verilog Canonical Sequential Network s(t+1) next state State Register x(t) present input Combinational Network clr clk always @(present_state or x) s(t) present state present z(t) output always @(posedge clk or posedge clr)

Verilog Mealy Machine always @(present_state or x) s(t+1) C 1 x(t) present input next state State Register clr s(t) present state always @(present_state or x) clk always @(posedge clk or posedge clr) z(t) C 2

Verilog Moore Machine s(t+1) C 1 x(t) present input next state State Register clr z(t) s(t) present state C 2 always @(present_state or x) clk always @(present_state or x) always @(posedge clk or posedge clr)

Sequence Detectors • Mealy and Moore Machines • A Sequence Detector using D Flip-flops • Verilog Program

Example Detect input sequence 1101 din clk fsm dout clr din dout 1 0 1 1 0 0 0 0 1 0

Creating a State Diagram Detect input sequence 1101 0 S 1 0 1 S 0 0 CLR 0 S 11 0 0 0 1 1 1 0 S 1101 1 1 S 110 0

Sequence Detectors • Mealy and Moore Machines • A Sequence Detector using D Flip-flops • Verilog Program

seqdet. v din clk seqdet dout clr // Sequence detector -- Detect 1101 module seqdet(clk, clr, din, dout); input clk, clr, din; output dout; reg dout;

seqdet. v reg[2: 0] present_state, next_state; clr din dout parameter S 0 = 3'b 000, S 1 =3'b 001, S 11 = 3'b 010, S 110 = 3'b 011, S 1101 = 3'b 100;

seqdet. v always @(posedge clk or posedge clr) begin if (clr == 1) present_state <= S 0; else present_state <= next_state; end clr din dout

seqdet. v // C 1: Next State 0 always @(present_state or din) 1 S 0 begin 0 0 case(present_state) S 0: if(din == 1) 0 CLR next_state <= S 1; 0 else next_state <= S 0; S 1101 S 1: if(din == 1) 1 next_state <= S 11; 1 else next_state <= S 0; S 11: if(din == 0) next_state <= S 110; else next_state <= S 11; S 110: if(din == 1) next_state <= S 1101; else next_state <= S 0; S 1101: if(din == 0) next_state <= S 0; else next_state <= S 11; default next_state <= S 0; endcase end S 1 0 1 S 110 0 0 1

seqdet. v // C 2: Outputs always @(present_state) begin if(present_state == S 1101) dout <=1; else dout <= 0; endmodule din clr dout

Detect input sequence 1101