ARM architecture Speaker Advisor 1 Outline n Features

ARM architecture Speaker: 陳 育 麟 Advisor: 陳 中 平 教授 1

Outline n Features n Core Interface Signals n 3 -stage pipeline organization n Programmer’s Mode n Conditional execution n A basic ARM memory system n ARM instruction set 2

Features n RISC core n Pipelined execution n Load-store architecture n Large uniform register file (R 0 ~ R 14) n Fixed-length instruction field n Conditional execution of all instructions 3

Core Interface Signals 4

3 -stage pipeline organization 5

3 -stage pipeline organization 6

3 -stage pipeline organization structural hazard! 7

Programmer’s Mode n Visible registers 8

Programmer’s Mode n CPSR I = 1: disable IRQ interrupt F = 1: disable FIQ interrupt Negative, Zero, Carry and o. Verflow T = 0: ARM execution T = 1: Thumb execution 9

Programmer’s Mode n Exception Vector Address Priorities 1 6 6 5 2 4 3 10

Conditional execution LOOP: … … BNE LOOP; 11

A basic ARM memory system data memory instruction memory 12

A basic ARM memory system n 4 -way low order interleaving Size = 1 KB 13

ARM instruction set n Branch n Data processing n Status register transferring n Load/Store n Coprocessor n Exception generating (SWI, BKPT) 14

ARM instruction set n B, BL 224 = 16 MB signed ± 8 MB 2 -bit interleaving ± 32 MB n Syntax B{L}{<cond>} <target_address> BL: the return address is stored in R 14. 15

ARM instruction set n BL usage … BL … SUB; branch ; return to here … SUB: … ; subroutine entry … MOV … CMP BLLT BLGE … R 0, #5; if R 0 < 5 ; (flag: N, Z, C and V) SUB 1; then call SUB 1 SUB 2; then call SUB 2 PC, R 14; return 16

Thank you! 17