32 bit parallel load register with clock gating

32 -bit parallel load register with clock gating Lan Luo ECE Department, 200 Broun Hall, Auburn University, Auburn, AL 36849, USA luolan 1@auburn. edu ELEC 6270 Project December 2007 1

Outline Concept of Power Dissipation & Clock Gating n Schematics of Basic Cells n Simulation Results n Conclusions n References n 2

n Dynamic Concept of Power Dissipation n Signal transitions (main source) n Logic activity n Glitches n Short-circuit n Static n Leakage 3

Clock Gating Technique n Clock signal is one of the main sources of chip power: - high switching activity - heavy capacitive loading of the clock network - clock signals in digital computers consume about 15 -45% of the system power n Solution: - deactivate the clock signal when there are no transitions on the flip-flops’ input 4

Clock Gating Circuit Latch free clock gating circuit Latch based clock gating circuit 5

n Design Platform n n n Latch based clock gating circuit used Technology: 0. 5µm Bi. CMOS process EDA Tool: Cadence Spectre (SPICE Simulator) f. CK = 50 MHz Power measurement n Current from power supply i. DD(t) is simulated n Average power Pavg(t) is calculated using integral 6

1 -bit non-clock-gating load register A 2 p. F/bit load capacitance CL is added to mimic typical clock signal load. 7

1 -bit clock-gating load register 8

Basic Cells - xor 2 9

Basic Cells - latch 10

Basic Cells - Flip-flop 11

Simulation Results n Case by case comparisons. n Typical case - Input vectors with random transitions n Best case - Input vectors with no transitions n Worst case - n Input vectors with transitions in each clock period Comparisons with different CL for typical case. n CL=0 p. F, 0. 025 p. F, 0. 125 p. F, 0. 5 p. F, 1. 5 p. F, 2. 5 p. F, 3 p. F 12

Typical Case (32 -bit) clock-gating non-clock-gating Power reduction: 53. 86% ! 13

Case by case comparisons n Typical case (→ typical benefit) n n Best case (→ best benefit) n n 9. 129 m. W→ 4. 212 m. W, power reduction is 53. 86% ! 9. 028 m. W→ 0. 802 m. W, power reduction is 91. 12% ! Worst case (→ least benefit) n 9. 661 m. W→ 9. 345 m. W, power reduction is 3. 27% ! 14

Power Comparison at different CL for typical case Overhead! 15

Power Reduction at different CL for typical case ? 16

Conclusions n Clock gating technique reduces dynamic power drastically. n The amount of power reduction is input data switching activity dependent. n The larger capacitive loading of clock signal, the more power reduction. 17

Reference n n n A. G. M. Strollo and D. De Caro, Low power flip-flop with clock gating on master and slave latches, ELECTRONICS LETTERS, Vol. 36, No. 4, 2000 Wu, Q. , Pedram, M. and Wu, X. , Clock-gating and its application to low power design of sequential circuits, CICC, 1997 Frank Emnett and Mark Biegel, Power Reduction Through RTL Clock Gating, SNUG 2000 Thanks ! 18