VLSI Testing Lecture 5 Logic Simulation Dr Vishwani

VLSI Testing Lecture 5: Logic Simulation Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical and Computer Engineering Auburn University, Alabama 36849, USA vagrawal@eng. auburn. edu http: //www. eng. auburn. edu/~vagrawal IIT Delhi, Aug 20, 2013, 2: 30 -3: 30 PM Copyright 2001, Agrawal & Bushnell Lecture 5: Logic Simulation 1

Contents n n What is simulation? Design verification Circuit modeling True-value simulation algorithms n n n Compiled-code simulation Event-driven simulation Summary Copyright 2001, Agrawal & Bushnell Lecture 5: Logic Simulation 2

Simulation Defined n n n Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification: n n Validate assumptions Verify logic Verify performance (timing) Types of simulation: n n Logic or switch level Timing Circuit Fault simulation (Lecture 6) Copyright 2001, Agrawal & Bushnell Lecture 5: Logic Simulation 3

Simulation for Verification Specification Synthesis Response analysis Design changes Computed responses Copyright 2001, Agrawal & Bushnell Design (netlist) True-value simulation Lecture 5: Logic Simulation Input stimuli 4

Modeling for Simulation n Modules, blocks or components described by n n Interconnects represent n n n Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gates, FET, resistors and capacitors ideal signal carriers, or ideal electrical conductors Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy. Copyright 2001, Agrawal & Bushnell Lecture 5: Logic Simulation 5

Example: A Full-Adder c a e d b HA f Half-adder A B C HA 1 D E HA 2 F Carry Sum Full-adder Copyright 2001, Agrawal & Bushnell Lecture 5: Logic Simulation HA; inputs: a, b; outputs: c, f; AND: A 1, (a, b), (c); AND: A 2, (d, e), (f); OR: O 1, (a, b), (d); NOT: N 1, (c), (e); FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA 1, (A, B), (D, E); HA: HA 2, (E, C), (F, Sum); OR: O 2, (D, F), (Carry); 6

Logic Model of MOS Circuit p. MOS FETs a b VDD Ca Cb Cc c a Da b Db n. MOS FETs Ca , Cb and Cc are parasitic capacitances Copyright 2001, Agrawal & Bushnell c Dc Da and Db are interconnect or propagation delays Dc is inertial delay of gate Lecture 5: Logic Simulation 7

Options for Inertial Delay Inputs (simulation of a NAND gate) Transient region a b Logic simulation c (CMOS) c (zero delay) c (unit delay) X c (multiple delay) Unknown (X) c (minmax delay) 0 Copyright 2001, Agrawal & Bushnell 5 Lecture 5: Logic Simulation rise=5, fall=5 min =2, max =5 Time units 8

Signal States n n Two-states (0, 1) can be used for purely combinational logic with zero-delay. Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. Four-states (0, 1, X, Z) are essential for MOS devices. See example below. Analog signals are used for exact timing of digital logic and for analog circuits. Z (hold previous value) 0 Copyright 2001, Agrawal & Bushnell 0 Lecture 5: Logic Simulation 9

Modeling Levels Timing Application 0, 1 Clock boundary Architectural and functional verification Connectivity of Boolean gates, flip-flops and transistors 0, 1, X and Z Zero-delay unit-delay, multipledelay Logic verification and test Switch Transistor size and connectivity, node capacitances 0, 1 and X Zero-delay Logic verification Timing Transistor technology data, connectivity, node capacitances Analog voltage Fine-grain timing Timing verification Circuit Tech. Data, active/ passive component connectivity Analog voltage, current Continuous time Digital timing and analog circuit verification Modeling level Circuit description Function, behavior, RTL Programming language-like HDL Logic Copyright 2001, Agrawal & Bushnell Signal values Lecture 5: Logic Simulation 10

True-Value Simulation Algorithms n Compiled-code simulation n n Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential circuits for logic verification Efficient for highly active circuits, but inefficient for lowactivity circuits High-level (e. g. , C language) models can be used Event-driven simulation n n Only gates or modules with input events are evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation Copyright 2001, Agrawal & Bushnell Lecture 5: Logic Simulation 11

Compiled-Code Algorithm n n n Step 1: Levelize combinational logic and encode in a compilable programming language Step 2: Initialize internal state variables (flip-flops) Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations) n Execute compiled code Report or save computed variables Copyright 2001, Agrawal & Bushnell Lecture 5: Logic Simulation 12

Event-Driven Algorithm (Example) 2 0 e =1 2 2 d=0 4 b =1 t=0 g =1 f =0 g 2 4 8 4 d, e d = 1, e = 0 f, g Time, t Lecture 5: Logic Simulation g=0 5 f=1 g 7 8 Copyright 2001, Agrawal & Bushnell c=0 3 6 0 Activity list 1 Time stack a =1 c =1 Scheduled events g=1 13

Efficiency of Event. Driven Simulator n n Simulates events (value changes) only Speed up over compiled-code can be ten times or more; in large logic circuits about 0. 1 to 10% gates become active for an input change Steady 0 0 → 1 event Copyright 2001, Agrawal & Bushnell Steady 0 (no event) Lecture 5: Logic Simulation Large logic block without activity 14

Summary n n n Logic or true-value simulators are essential tools for design verification. Verification vectors and expected responses are generated (often manually) from specifications. A logic simulator can be implemented using either compiled-code or event-driven method. Per vector complexity of a logic simulator is approximately linear in circuit size. Modeling level determines the evaluation procedures used in the simulator. Copyright 2001, Agrawal & Bushnell Lecture 5: Logic Simulation 15