Final Design Review of a 1 GHz LNA

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Final Design Review of a 1 GHz LNA / Down-Converter Charles Baylis University of

Final Design Review of a 1 GHz LNA / Down-Converter Charles Baylis University of South Florida April 22, 2005

LNA Design Summary n n n IBM Si. Ge Design Kit - 4 layers

LNA Design Summary n n n IBM Si. Ge Design Kit - 4 layers of metal Load resistance = 50 ohms (Filter) Feedback Resistor from collector to base stabilizes circuit, provides better matching For feedback configuration IC = 6 m. A, RF = 460 ohms (initial – values were changed for final schematic.

LNA Design Summary n n n Power Consumption: Current through gain transistor + 1

LNA Design Summary n n n Power Consumption: Current through gain transistor + 1 m. A reference current through current mirror. LC Match on Input/Output “De-Q” Inductors with resistors to improve bandwidth.

LNA Schematic Vcc 7. 3 n. H 1. 4 kΩ 560 Ω 27 p.

LNA Schematic Vcc 7. 3 n. H 1. 4 kΩ 560 Ω 27 p. F 6. 5 n. H 9. 3 p. F 83 p. F Input Ground 650 Ω 4. 5 p. F Output

LNA Gain

LNA Gain

LNA Noise Figure

LNA Noise Figure

LNA Input IP 3

LNA Input IP 3

LNA Input/Output Match

LNA Input/Output Match

LNA Compliance Reqt. Spec. Min Spec. Max Minimum Maximum - 10 m. A -

LNA Compliance Reqt. Spec. Min Spec. Max Minimum Maximum - 10 m. A - 9. 8 m. A Pass 14. 5 d. B 17. 5 d. B 16. 9 d. B Pass - 2. 5 d. B 2. 3 d. B 2. 8 d. B Fail Input IP 3 -20 d. Bm - -2. 7 d. Bm - Pass Uncond. Stability - - Pass Input Return Loss 15. 0 d. B - 15. 7 d. B 20. 9 d. B Pass Output Return Loss 15. 0 d. B - 15. 0 d. B 30. 3 d. B Pass DC Current Gain Noise Figure Pass/Fail

LNA Compliance-Temperature Reqt. DC Current Spec. Min Spec. Max Minimum Maximum Pass/Fai l -

LNA Compliance-Temperature Reqt. DC Current Spec. Min Spec. Max Minimum Maximum Pass/Fai l - 10 m. A 9. 3 m. A (-20˚) 10. 2 m. A (70˚) Fail 14. 5 d. B 17. 5 d. B 16. 0 d. B (70˚) 17. 5 d. B (-20˚) Pass Noise Figure - 2. 5 d. B 1. 93 d. B (-20˚) 3. 24 d. B (70˚) Fail Uncond. Stability - - Pass Input Return Loss 15. 0 d. B - 14. 7 d. B (-20˚) 21. 6 d. B (70˚) Fail Output Return Loss 15. 0 d. B - 14. 0 d. B (70˚) 31. 4 d. B (-20˚) Fail Gain

LNA Compliance - Bias Reqt. DC Current Spec. Min Spec. Max Minimum - 10

LNA Compliance - Bias Reqt. DC Current Spec. Min Spec. Max Minimum - 10 m. A 14. 5 d. B 17. 5 d. B 14. 9 d. B (2. 7 V) Noise Figure - 2. 5 d. B Uncond. Stability - Input Return. Loss Output Return. Loss Gain Maximum 8. 1 m. A (2. 7 V) 11. 6 m. A (3. 3 V) Pass/Fail 18. 0 d. B (3. 3 V) Fail 2. 3 d. B (3. 3 V) 2. 9 d. B (2. 7 V) Fail - - - Pass 15. 0 d. B - 12. 9 d. B (3. 3 V) 22. 2 d. B (3. 3 V) Fail 15. 0 d. B - 10. 7 d. B (2. 7 V) 30. 3 d. B (3 V) Fail

LNA Layout LNA Out LNA In Vcc

LNA Layout LNA Out LNA In Vcc

Mixer Design Approach n n n f. RF = 1 GHz, f. LO =

Mixer Design Approach n n n f. RF = 1 GHz, f. LO = 860 MHz, f. IF = 140 MHz Conversion gain = 9 d. B = 2. 82 Output Resistance = 50 Ω RL= 25 Ω Solve conversion gain equation for gm (gives starting value for current IC 1). . Use LC network for input matching.

Mixer Design Approach n n Noise figure improved by shrinking reference transistor for current

Mixer Design Approach n n Noise figure improved by shrinking reference transistor for current mirror (and associated current). Also, beta helper transistor size was increased. As in LNA, “de-Q” inductors with shunt resistors to improve bandwidth.

Mixer Schematic Vcc 7. 03 kΩ LO+ Out - LO- 7 kΩ 7. 8

Mixer Schematic Vcc 7. 03 kΩ LO+ Out - LO- 7 kΩ 7. 8 n. H Input 3. 7 p. F 83 p. F 250 Ω Ground

Mixer Conversion Gain

Mixer Conversion Gain

Mixer Input IP 3

Mixer Input IP 3

Mixer Input/Output Match Input Reflection Coefficient Output Reflection Coefficient

Mixer Input/Output Match Input Reflection Coefficient Output Reflection Coefficient

Mixer Noise Figure

Mixer Noise Figure

Mixer Compliance Reqt. DC Current Gain Noise Figure Input IP 3 Input Return Loss

Mixer Compliance Reqt. DC Current Gain Noise Figure Input IP 3 Input Return Loss Output Return Loss Spec. Min Spec. Max Minimum Maximum - 25 m. A - 12. 4 m. A Pass 7. 5 d. B 10. 5 d. B 9. 3 d. B 10. 0 d. B Pass - 11 d. B 9. 0 d. B 10. 7 d. B Pass - Pass 26. 4 Pass 31. 2 d. B Pass -15 d. Bm -12. 95 Specified Gain and Bandwidth 15. 0 d. B 15. 2 d. B 15. 0 d. B - 31. 5 d. B Pass/Fail

Mixer Compliance - Temperature Reqt. DC Current Gain Noise Figure Spec. Min Spec. Max

Mixer Compliance - Temperature Reqt. DC Current Gain Noise Figure Spec. Min Spec. Max Minimum Maximum - 25 m. A 11. 47 m. A 13. 3 m. A Pass 7. 5 d. B 10. 5 d. B 7. 9 d. B 11. 1 d. B Fail - 11 d. B 7. 1 d. B 11. 59 d. B Fail 31. 7 Fail 31. 6 d. B Pass Input Return Loss 15. 0 d. B Specified Gain and Bandwidth Output Return Loss 15. 0 d. B - 31. 2 d. B Pass/Fail

Mixer Compliance - Bias Reqt. DC Current Gain Noise Figure Spec. Min Spec. Max

Mixer Compliance - Bias Reqt. DC Current Gain Noise Figure Spec. Min Spec. Max Minimum Maximum - 25 m. A 9. 9 m. A 15. 1 m. A Pass 7. 5 d. B 10. 5 d. B 8. 2 d. B 10. 7 d. B Fail - 11 d. B 7. 9 d. B 10. 9 d. B Pass 45. 4 Fail 40. 2 d. B Pass Input Return Loss 15. 0 d. B 13. 7 d. B Specified Gain and Bandwidth Output Return Loss 15. 0 d. B - 27. 8 d. B Pass/Fail

Mixer Layout Mixer In Vcc Out + Out - LO +- LO -

Mixer Layout Mixer In Vcc Out + Out - LO +- LO -

LNA DRC and LVS

LNA DRC and LVS

Mixer DRC and LVS

Mixer DRC and LVS

Conclusion n n Only LNA noise figure does not meet specification at nominal temperature

Conclusion n n Only LNA noise figure does not meet specification at nominal temperature and bias. Design has been run through multiple simulations to test its robustness.