ECE 361 Computer Architecture Lecture 11 Designing a

ECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller 361 multicontroller. 1

Review of a Multiple Cycle Implementation ° The root of the single cycle processor’s problems: • The cycle time has to be long enough for the slowest instruction ° Solution: • Break the instruction into smaller steps • Execute each step (instead of the entire instruction) in one cycle - Cycle time: time it takes to execute the longest step - Keep all the steps to have similar length • This is the essence of the multiple cycle processor ° The advantages of the multiple cycle processor: • Cycle time is much shorter • Different instructions take different number of cycles to complete - Load takes five cycles - Jump only takes three cycles • Allows a functional unit to be used more than once per instruction 361 multicontroller. 2

Review: Instruction Fetch Cycle, In the Beginning ° Every cycle begins right AFTER the clock tick: • mem[PC] PC<31: 0> + 4 Clk One “Logic” Clock Cycle You are here! PCWr=? PC Mem. Wr=? 32 IRWr=? Instruction Reg Clk 32 RAdr Ideal Memory 32 32 Wr. Adr Din Dout ALU 32 4 32 32 32 ALU Control ALUop=? Clk 361 multicontroller. 3 32

Review: Instruction Fetch Cycle, The End ° Every cycle ends AT the next clock tick (storage element updates): • IR <-- mem[PC] PC<31: 0> <-- PC<31: 0> + 4 Clk One “Logic” Clock Cycle You are here! PCWr=1 PC 32 Mem. Wr=0 IRWr=1 ALU 32 00 32 32 32 Instruction Reg Clk RAdr Ideal Memory Wr. Adr Din Dout 4 32 32 ALU Control ALUOp = Add 32 Clk 361 multicontroller. 4 32

Putting it all together: Multiple Cycle Datapath PCWr. Cond Zero Mem. Wr ALUSel. A Reg. Wr 1 1 Wr. Adr 32 Din Dout 32 32 32 Rt 0 5 Rd Mux Ideal Memory Rt 5 Rb bus. A Reg File 32 bus. W bus. B 32 1 Extend Ext. Op 32 1 Rw 1 Mux 0 Imm 16 361 multicontroller. 5 Ra << 2 4 0 1 32 32 2 3 32 Memto. Reg Zero ALU Mux RAdr Rs Target 32 0 0 Mux 0 Instruction Reg 32 32 Reg. Dst 32 PC 32 IRWr Br. Wr Mux Ior. D PCSrc ALU Control ALUOp ALUSel. B

Instruction Fetch Cycle: Overall Picture Ifetch ALUOp=Add 1: PCWr, IRWr x: PCWr. Cond Reg. Dst, Mem 2 R Others: 0 s PCWr=1 Wr. Adr 32 Din Dout 32 bus. A 4 bus. B 32 32 ALUSel. B=00 361 multicontroller. 6 Zero 0 1 2 3 Target 32 32 1 ALU Ideal Memory 1 Mux RAdr Instruction Reg 0 Br. Wr=0 0 0 32 32 ALUSel. A=0 32 PCSrc=0 Mux PCWr. Cond=x Zero Ior. D=0 Mem. Wr=0 IRWr=1 32 32 ALU Control ALUOp=Add

Register Fetch / Instruction Decode (Continue) Rfetch/Decode ° bus. A <- Reg[rs] ; bus. B <- Reg[rt] ; ALUOp=Add 1: Br. Wr, Ext. Op ALUSel. B=10 x: Reg. Dst, PCSrc Ior. D, Memto. Reg Others: 0 s ° Target <- PC + Sign. Ext(Imm 16)*4 PCWr=0 ALUSel. A=0 1 Wr. Adr 32 Din Dout 32 32 Rt 0 5 Rd 32 Beq Rtype Ori Memory Mux Ideal Memory Rt 5 Ra Rb bus. A Reg File Rw bus. W bus. B 32 1 << 2 Control Op Func : 361 multicontroller. 7 6 6 Imm 16 Extend Ext. Op=1 4 Zero 0 1 2 3 Target 32 32 1 ALU Mux RAdr Rs Br. Wr=1 0 0 Mux 0 Instruction Reg 32 32 Reg. Wr=0 32 PC 32 Reg. Dst=x PCSrc=x Mux PCWr. Cond=0 Zero Ior. D=x Mem. Wr=0 IRWr=0 32 32 ALU Control ALUSel. B=10 32 ALUOp=Add

R-type Execution RExec 1: Reg. Dst ALUSel. A ALUSel. B=01 ALUOp=Rtype x: PCSrc, Ior. D Memto. Reg Ext. Op ° ALU Output <- bus. A op bus. B PCWr=0 ALUSel. A=1 1 Wr. Adr 32 Din Dout 32 32 32 Rt 0 5 Rd Mux Ideal Memory Rt 5 Rb bus. A Reg File 32 4 bus. W bus. B 32 1 Extend Ext. Op=x << 2 32 Memto. Reg=x Zero 0 1 2 3 Target 32 32 1 Rw 1 Mux 0 Imm 16 361 multicontroller. 8 Ra 1 ALU Mux RAdr Rs Br. Wr=0 0 0 Mux 0 Instruction Reg 32 32 Reg. Wr=0 32 PC 32 Reg. Dst=1 PCSrc=x Mux PCWr. Cond=0 Zero Ior. D=x Mem. Wr=0 IRWr=0 32 32 ALU Control ALUOp=Rtype ALUSel. B=01

R-type Completion Rfinish ALUOp=Rtype 1: Reg. Dst, Reg. Wr ALUsel. A ALUSel. B=01 x: Ior. D, PCSrc Ext. Op ° R[rd] <- ALU Output PCWr=0 ALUSel. A=1 1 Wr. Adr 32 Din Dout 32 32 32 Rt 0 5 Rd Mux Ideal Memory Rt 5 Rb bus. A Reg File 32 4 bus. W bus. B 32 1 Extend Ext. Op=x << 2 32 Memto. Reg=0 Zero 0 1 2 3 Target 32 32 1 Rw 1 Mux 0 Imm 16 361 multicontroller. 9 Ra 1 ALU Mux RAdr Rs Br. Wr=0 0 0 Mux 0 Instruction Reg 32 32 Reg. Wr=1 32 PC 32 Reg. Dst=1 PCSrc=x Mux PCWr. Cond=0 Zero Ior. D=x Mem. Wr=0 IRWr=0 32 32 ALU Control ALUOp=Rtype ALUSel. B=01

Outline of Today’s Lecture ° Recap ° Review of FSM control ° From Finite State Diagrams to Microprogramming 361 multicontroller. 10

Overview ° Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing Control Function Explicit Next State + Dispatch ROMs Microprogram counter Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM “hardwired control” 361 multicontroller. 11 “microprogrammed control”

Initial Representation: Finite State Diagram 0 2 Adr. Cal Ifetch 1: Ext. Op ALUSel. A ALUSel. B=11 ALUOp=Add x: Memto. Reg PCSrc lw 3 sw ALUSel. A, Ior. D ALUSel. B=11 ALUOp=Add x: Memto. Reg PCSrc LWwr 361 multicontroller. 12 1: ALUSel. A Reg. Wr, Ext. Op Memto. Reg ALUSel. B=11 ALUOp=Add x: PCSrc Ior. D 5 SWMem 6 1: Ext. Op Mem. Wr ALUSel. A ALUSel. B=11 ALUOp=Add x: PCSrc, Reg. Dst Memto. Reg 8 Rfetch/Decode ALUOp=Add 1: Br. Wr, Ext. Op ALUSel. B=10 x: Reg. Dst, PCSrc Ior. D, Memto. Reg Others: 0 s lw or sw 1: Ext. Op LWmem 4 1 ALUOp=Add 1: PCWr, IRWr x: PCWr. Cond Reg. Dst, Mem 2 R Others: 0 s beq Ori Rtype RExec 1: Reg. Dst ALUSel. A ALUSel. B=01 ALUOp=Rtype x: PCSrc, Ior. D Memto. Reg Ext. Op Br. Complete ALUOp=Sub ALUSel. B=01 x: Ior. D, Mem 2 Reg Reg. Dst, Ext. Op 1: PCWr. Cond ALUSel. A PCSrc 10 Ori. Exec ALUOp=Or 1: ALUSel. A ALUSel. B=11 x: Memto. Reg Ior. D, PCSrc 11 7 Rfinish ALUOp=Rtype 1: Reg. Dst, Reg. Wr ALUsel. A ALUSel. B=01 x: Ior. D, PCSrc Ext. Op Ori. Finish ALUOp=Or x: Ior. D, PCSrc ALUSel. B=11 1: ALUSel. A Reg. Wr

Sequencing Control: Explicit Next State Function Control Logic Inputs Opcode O u t p u t s State Reg ° Next state number is encoded just like datapath controls 361 multicontroller. 13 Multicycle Datapath

Logic Representative: Logic Equations ° Next state from current state • State 0 -> State 1 • State 1 -> S 2, S 6, S 8, S 10 • State 2 ->_____ • State 3 ->_____ • State 4 ->State 0 • State 5 -> State 0 • State 6 -> State 7 • State 7 -> State 0 • State 8 -> State 0 • State 9 -> State 0 • State 10 -> State 11 • State 11 -> State 0 361 multicontroller. 14 °Alternatively, prior state & condition S 4, S 5, S 7, S 8, S 9, S 11 -> State 0 _________ -> State 1 _________ -> State 2 _________ -> State 3 _________ -> State 4 State 2 & op = sw -> State 5 _________ -> State 6 -> State 7 _________ -> State 8 State 2 & op = jmp -> State 9 _________ -> State 10 -> State 11

Implementation Technique: Programmed Logic Arrays ° Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane Op 5 Op 4 Op 3 Op 2 Op 1 Op 0 S 3 S 2 S 1 S 0 0 = 0000 6 = 0110 1 = 0001 7 = 0111 2 = 0010 8 = 1000 3 = 0011 9 = 1001 4 = 0100 10 = 1010 5 = 0101 11 = 1011 361 multicontroller. 15 R = 000000 beq = 000100 lw = 100011 sw = 101011 ori = 001011 jmp = 000010 NS 3 NS 2 NS 1 NS 0

Implementation Technique: Programmed Logic Arrays ° Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane Op 5 Op 4 Op 3 Op 2 Op 1 Op 0 S 3 S 2 S 1 S 0 0 = 0000 6 = 0110 1 = 0001 7 = 0111 2 = 0010 8 = 1000 3 = 0011 9 = 1001 4 = 0100 10 = 1010 5 = 0101 11 = 1011 361 multicontroller. 16 lw = 100011 sw = 101011 R = 000000 ori = 001011 beq = 000100 jmp = 000010 NS 3 NS 2 NS 1 NS 0

Multicycle Control ° Given numbers of FSM, can turn determine next state as function of inputs, including current state ° Turn these into Boolean equations for each bit of the next state lines ° Can implement easily using PLA ° What if many more states, many more conditions? ° What if need to add a state? 361 multicontroller. 17

Next Iteration: Using Sequencer for Next State ° Before Explicit Next State: Next try variation 1 step from right hand side ° Few sequential states in small FSM: suppose added floating point? ° Still need to go to non-sequential states: e. g. , state 1 => 2, 6, 8, 10 Initial Representation Finite State Diagram Microprogram Sequencing Control Function Explicit Next State + Dispatch ROMs Microprogram counter Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM “hardwired control” 361 multicontroller. 18 “microprogrammed control”

Sequencer-based control unit Control Logic Multicycle Datapath Outputs Inputs 1 Adder Types of “branching” • Set state to 0 • Dispatch (state 1 & 2) • Use incremented state number State Reg Address Select Logic Opcode 361 multicontroller. 19

Sequencer-based control unit details Control Logic Inputs 1 Adder State Reg 3 2 Mux 1 0 Address Select Logic ROM 2 0 ROM 1 Opcode 361 multicontroller. 20 Dispatch ROM 1 Op Name State 000000 Rtype 0110 000010 jmp 1001 000100 beq 1000 001011 ori 1010 100011 lw 0010 101011 sw 0010 Dispatch ROM 2 Op Name State 100011 lw 0011 101011 sw 0101

Implementing Control with a ROM ° Instead of a PLA, use a ROM with one word per state (“Control word”) State number 0 1 2 3 4 5 6 7 8 9 10 11 361 multicontroller. 21 Control Word Bits 18 -2 Control Word Bits 1 -0 10010100000001000 0000010011000 00000010100 0011000010100 00110010000010110 00101000000010100 00000000001000111 01000000100100100 1000000000 … 11 … 00 11 01 10 11 00 00 00

Next Iteration: Using Microprogram for Representation Initial Representation Finite State Diagram Microprogram Sequencing Control Function Explicit Next State + Dispatch ROMs Microprogram counter Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM “hardwired control” “microprogrammed control” ° ROM can be thought of as a sequence of control words ° Control word can be thought of as instruction: “microinstruction” ° Rather than program in binary, use assembly language 361 multicontroller. 22

Microprogramming ° Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer 361 multicontroller. 23

Macroinstruction Interpretation Main Memory ADD SUB AND . . . DATA execution unit CPU control memory User program plus Data this can change! one of these is mapped into one of these AND microsequence e. g. , Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) 361 multicontroller. 24

Microprogramming Pros and Cons ° Ease of design ° Flexibility • Easy to adapt to changes in organization, timing, technology • Can make changes late in design cycle, or even in the field ° Can implement very powerful instruction sets (just more control memory) ° Generality • Can implement multiple instruction sets on same machine. • Can tailor instruction set to application. ° Compatibility • Many organizations, same instruction set ° Costly to implement ° Slow 361 multicontroller. 25

Summary: Multicycle Control ° Microprogramming and hardwired control have many similarities, perhaps biggest difference is initial representation and ease of change of implementation, with ROM generally being easier than PLA Initial Representation Finite State Diagram Microprogram Sequencing Control Function Explicit Next State + Dispatch ROMs Microprogram counter Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM “hardwired control” 361 multicontroller. 26 “microprogrammed control”