De Morgans Law and Gates CMPE 212 Discussion

De. Morgan’s Law and Gates CMPE 212 Discussion Patrick Sykes

In Lab Today n Learn how to use the function generator and oscilloscope. n We’ll connect the function generator and oscilloscope to check gate time delays.

Digital Design n So far in class, we have covered number systems and some logic gates. n Maybe you’re wondering the application of said gates? n So we’ll build a circuit that actually has an application

Mystery Circuit

Verilog Practice n We will be revisiting this circuit several times throughout the semester. n Try to implement this circuit in Verilog.

Time Delay n There is currently a speed limit to our signals n This causes a delay from the input of a circuit to the output n For our purposes so far, the time delay is so short we don’t notice it.

Time Delay n Critical path: The longest necessary path through a circuit n In lab, we want to exaggerate the critical path n We will eventually see an example with a large critical path, related to our mystery circuit n There are ways to deal with this, which you will learn in class

De. Morgan’s Laws n Get used to them because they’ll be very useful

Upcoming Homework n Implement modules in Verilog that demonstrate De. Morgan’s Laws n You will be given a testbench and makefile, it is up to you to create a file that works with them n The diagrams on the previous slide should show you all the modules you have to implement

Questions?