CPU 08 INTRODUCTION M CPU 08 Core Execution

CPU 08 INTRODUCTION M CPU 08 Core Execution Architecture MTT 48 3 -1

CPU 08 Clock Generation Module (CGM) System Integration Module (SIM) LVI IRQ RESET COP 68 HC 08 CPU BREAK Timer Interface Module (TIM) Direct Memory Access Module (DMA) Internal Bus (IBUS) Serial Communications Interface (SCI) M Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable Memory (EPROM) Monitor ROM CPU 08 Core Execution Architecture MTT 48 3 -3

Module Exercise Objectives At end of sections coming up, will write • Subroutine that clears all RAM locations • Code sequence that executes at Power-on or RESET and calls the RAM clearing subroutine M CPU 08 Core Execution Architecture MTT 48 3 -4

CPU 08 EXECUTION ARCHITECTURE M CPU 08 Core Execution Architecture MTT 48 3 -5

CPU 08 Execution Architecture CPU 08 is divided into two blocks • Control unit – Contains a finite state machine, control and timing units that drive the execution unit • Execution unit – Contains the ALU, registers, and bus interface M CPU 08 Core Execution Architecture MTT 48 3 -6

CPU 08 Prefetch HC 05 has many cycles where the address and data bus are idle CPU 08 contains an opcode "look ahead" prefetch mechanism • Performance increases were achieved by removing as many dead bus cycles as possible. CPU 08 instruction flow was developed to be as efficient as possible in a pipelined architecture M CPU 08 Core Execution Architecture MTT 48 3 -7

Instruction Execution All instructions: • Execute in a finite number of bus cycles – See individual instructions for number of bus cycles • Load next opcode into Opcode Lookahead register • Increment the Program Counter to next location – Happens after prefetch – Program Counter will be pointing to byte following prefetched opcode M CPU 08 Core Execution Architecture MTT 48 3 -8

Control Signals Two Control Unit signals control prefetch and instruction loading • Opcode Lookahead – Signals prefetch operation • Lastbox – Signals last cycle of current instruction M CPU 08 Core Execution Architecture MTT 48 3 -9

Programming Model Accumulator (A) Index Register (H: X) Stack Pointer (SP) Program Counter (PC) Condition Code Register (CCR) M CPU 08 Core Execution Architecture MTT 48 3 - 10

Condition Code Registers Bits V - Two’s complement overflow flag • Set if a signed arithmetic operation has overflowed • Utilized in checking signed arithmetic operations H - Half Carry flag • Set if a carry occurred from bit 3 to bit 4 • Utilized in Binary Code Decimal (BCD) operations I - Global Interrupt Mask • When set, disables CPU interrupts N - Negative • Set if bit 7 is set in the Accumulator Z - Zero flag • Set if all bits in the Accumulator are clear C - Carry or Borrow flag M • Set if a carry or borrow occurred during an operation CPU 08 Core Execution Architecture MTT 48 3 - 11

M CPU 08 Core Execution Architecture MTT 48 3 - 12