CMX firmware development Pawel Plucinski Stockholm University CMX
- Slides: 11
CMX firmware development Pawel Plucinski Stockholm University CMX firmware status G-Link and GTX serializer Clock manager Memory Conclusions
CMM code – the port to the V 6 Recent changes and tests CMM code – the port to the V 6. This includes: Two versions: VC and VS. G-link emulation + serializer GTX (including ISIM and scope tests of the optical output; target ML 605 - xc 6 vlx 240 t). Adapting the clock tree to the Virtex-6 MMCM. Updating the block RAM implementation in the readout fifo/memory. Successfully simulated (ISIM).
G-link emulation in Virtex 6 General idea DAQ or ROI data word 20 b G-link encoder Encoded word 24 b 8 b multiplexer 8 b GTX TX DAV (data available) 40 MHz 120 MHz 960 Mbs
G-link emulation in Virtex 6 The readout scheme DAQ_IN daq_enc DAQ_DAV 20 b G-link encoder DAQ_RST clk 40 daq_byte daq_out 24 b clk 40 8 b clk 120 2 b GTX TX Mux ROI_IN roi_enc ROI_DAV 20 b G-link encoder ROI_RST clk 40 clk 120 clk 40 roi_byte roi_out 24 b clk 40 8 b clk 120 GTX TX 2 b
G-link emulation in Virtex 6 Behavioral simulation results Reset DAV asserted non zeros data Empty frames Sending zeros This test was done with Xilinx ISIM. . .
G-link emulation in Virtex 6 “An eye diagram” Scope tests of the optical output (target ML 605): Good result: Rise and Fall time below 240 psec!
CMM code – the port to the V 6 Adapting the clock tree (MMCM)
CMM code – the port to the V 6 Updating the block RAM Memory type: True Dual Port RAM Write/Read Width: 16 b Write/Read Depth: 256
CMM code – the port to the V 6 Simulation results: cmm_jepcrt_vc No errors DAQ data Testbench with random input data (no errors).
CMM code – the port to the V 6 Simulation results: cmm_jepcrt_vs Readout enable DAQ and ROI data No errors Testbench with random input data (no errors).
Conclusion 'Jet-CMM emulation' design for Virtex-6 on the CMX: two versions 'vc' and 'vs', available on SVN. G-link protocol + GTX serializer is added The Clock tree is updated. The clock manager (MMCM) is being used. 'A new block RAM' in the readout fifo/memory implemented. Design was successfuly simulated with ISIM (testbunch, random input data, no errors). Latency is unchanged.
