CISC Complex Instruction Set Computer Veeraraghavan Ramamurthy ELEC

CISC (Complex Instruction Set Computer) Veeraraghavan Ramamurthy ELEC 6200 Computer Architecture and Design Fall 2005 11/11/05 ELEC 6200 -001 1

What is CISC? A complex instruction set computer is a microprocessor instruction set architecture (ISA) in which each instruction can execute several low-level operations such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. Most common microprocessor designs --- including the Intel 80 x 86 and Motorola 68 K series --- also follow the CISC philosophy. 11/11/05 ELEC 6200 -001 2

CISC philosophy Ø use microcode Ø build rich instruction sets Ø build high-level instruction sets 11/11/05 ELEC 6200 -001 3

Characteristics of a CISC design Instruction sets The design constraints that led to the development of CISC (small amounts of slow memory, and the fact that most early machines were programmed in assembly language) give CISC instruction sets some common characteristics: A 2 -operand format, where instructions have a source and a destination. For example, consider the add instruction "add #5, D 0“ Register to register, register to memory, and memory to register commands. 11/11/05 ELEC 6200 -001 4

Characteristics of a CISC design Multiple addressing modes for memory, including specialized modes for indexing through arrays Variable length instructions where the length often varies according to the addressing mode Instructions which require multiple clock cycles to execute. 11/11/05 ELEC 6200 -001 5

Hardware architectures Most CISC hardware architectures have several characteristics in common: Complex instruction-decoding logic. A small number of general purpose registers. Several special purpose registers. Many CISC designs set aside special registers for the stack pointer, interrupt handling, and so on. This can simplify the hardware design somewhat, at the expense of making the instruction set more complex. 11/11/05 ELEC 6200 -001 6

Hardware architectures A "Condition code" register which is set as a sideeffect of most instructions. This register reflects whether the result of the last operation is less than, equal to, or greater than zero, and records if certain error conditions occur. 11/11/05 ELEC 6200 -001 7

The ideal CISC machine n n n CISC processors were designed to execute each instruction completely before beginning the next instruction. An instruction is fetched from main memory. The instruction is decoded. The instruction is executed. The results are written to memory. 11/11/05 ELEC 6200 -001 8

A realistic CISC machine n In reality, some instructions may require more than one clock per stage. However, a CISC design can tolerate this slowdown since the idea behind CISC is to keep the total number of cycles small by having complicated things happen within each cycle. 11/11/05 ELEC 6200 -001 9

CISC and the Classic Performance Equation n The usual equation for determining performance is the sum for all instructions of (the number of cycles per instruction * instruction cycle time) = execution time. This allows you to speed up a processor in 3 different ways -- use fewer instructions for a given task, reduce the number of cycles for some instructions, or speed up the clock (decrease the cycle time. ) n CISC tries to reduce the number of instructions for a program, and RISC tries to reduce the cycles per instruction. 11/11/05 ELEC 6200 -001 10

The advantages of CISC n supports higher-level languages smaller program sizes fewer calls to main memory n less RAM needed n n 11/11/05 ELEC 6200 -001 11

The disadvantages of CISC n n n greater overhead in decoding instructions, therefore slowdown of execution designing the chips requires more work harder to use registers efficiently higher power consumption many specialized instructions aren't used frequently enough to justify their existence --- approximately 20% of the available instructions are used in a typical program. 11/11/05 ELEC 6200 -001 12