Chapter 2 Test Specification Process n Device Specification

Chapter 2 Test Specification Process

n Device Specification Sheet – Purpose n Design – Determine functionality of design n Test – Specification List Generation Insure device lives up to spec sheet claims n Communication – Verify that device is appropriate for the end application n Flexible – – – Document Ownership - catalog or custom? Allows changes to specifications Avoid ambiguities n Late Changes in Specification Sheet Indicates Poor Organization

n Device Specification Sheet – Structure n Feature – Summary Quick look at functionality of chip n Principles – Detailed device function • guaranteed by functional or parametric test program n Absolute – – – Maximum Ratings Failure limits of chip • not critical to a test engineer n Electrical – of Operation Specifications Core of parametric tests Test conditions are listed as notes MAX, MIN, TYP, guaranteed by design

n Device Specification Sheet – Structure n Timing – – Diagrams Critical to test program development Manually generated for frequency synchronization n Application – – Information Aids customer in designing end application Functional block diagram • shows top level representation of device function n Characterization – Data collected during testing i. e. parameter histograms n Circuit – Data Schematics / Die Layout Device functional pin representation and layout

n Generating the Test Plan – To Plan or Not to Plan? n Shoot – – From the Hip Approach Non-optimized May cause a device to be Non-testable n Planned – – Testing Allows early interaction between design and test engineers Identification of non-testable functions Synchronization of clocking schemes Tester hardware identification • identify tester hardware deficiencies

n Generating the Test Plan – Purpose of a Test Plan n Less Formal than a Device Data Sheet n Test Engineers Roadmap to Generate Test Program n Official Communication Tool – – © 2000 R. J. Fink Test engineer Design engineer Product engineer Customer

n Generating the Test Plan – Structure of a Test Plan n Device Background not Found in Data Sheet n Special Test Requirements n Explanation of the Purpose of Each Test n Assumptions regarding particular test and why n Hardware Setup Diagram for each Test n All Documentation should be Tester Independent n Tester Specific Information should be added as a separate section

n Generating the Test Plan – Design Specifications vs. Production Test Specifications n Production Testing is very Time Critical!! n Not all Design Parameters need to be Tested in Production n Identification of Critical Test Parameters n Minimum Testing to Reduce Test Time while Insuring Device Functionality

n Generating the Test Plan – Converting the Spec Sheet into a Test Plan n Infinite Permutations of Possible Tests Indicated by Data Sheet n Caution is necessary due to signal interactions n How does the Test Engineer know which Tests are needed in Production Testing? ? – – For each sentence in the device description, there should be at least one test that verifies the claim Max. and Min. electrical specifications must all be verified Worst case failure modes are often used to limit the number of tests required to verify the device function Extensive testing of a device will reveal more tests which need to be added or can be omitted

n Components of a Test Plan – Test Program Structure n Coded – – – – – Version of the Test Plan Waveform creation / Tester initializations Calibrations Continuity DC parametric tests AC parametric tests Functional tests / Digital patterns Digital timing tests Test sequence control Test limits Binning control

n Components of a Test Plan – Test Code and Digital Patterns n Test – Code Controls order and timing - does not create timing signal • instrument settings • signal generation • signal measurements n Digital – – Patterns Consists of groups of data called vectors • drive data for each pin • expect data for each pin Vectors are sent out at a regular rate “bit cell rate” Tight frequency control is critical Allow looping and branching of vectors

n Components of a Test Plan – Binning n Grading – – Performed by handler Pass or Fail Continuity Fail - could indicate handler error Different grades of device based upon performance • 100 MHz chip vs 120 MHz chip n Fast – – of Devices into “Bins” Binning Device is rejected as soon as it fail first test Reduces test time

n Components of a Test Plan – Test Sequence Control n Sequencers – – C program coded Graphical user interface controlled n Waveform Calculations and Other Initializations n Pre-computed Waveforms – Performed only once when the program is loaded • tl_init function in Teradyne architecture n Reset – – © 2000 R. J. Fink of tester Instrumentation to Default State Focussed calibrations Checkers

n Components of a Test Plan – Focussed Calibrations n Tester does not have Sufficient Accuracy for a Test n Determines the Inaccuracy of a Fast Instrument using Slower, more Accurate Instrumentation – – Software compensation allows a more accurate result. Not absolutely perfect - still has the inaccuracy of the more accurate instrumentation n Software – Calibration due to DIB Design DIB Checkers n Checks for Faulty Op-Amps, Comparators, and Relays often placed on the DIB – Avoids running thousands of devices on a bad DIB board

n Components of a Test Plan – Characterization Code n Used for Characterization of First Production Devices n Very Thorough Testing to Identify and Correct Marginal Portions of the Design – Simulation Code n Added to Test Program to Allow Mathematical Routines to be Verified n Offline Debugging of Test Code – Avoids wasting valuable tester time

n Components of a Test Plan – Debuggability n Debugging Consumes 20% of a Test Engineers Week – – – Test code bugs Hardware errors Correlation errors Intermittent failures DIB errors Broken tester modules n Design – – Debugging Ability to modify code to isolate a device function Run experiments for designers or customers to verify device