ATLAS Upgrade Workshop Upgrade of the Tile CAL

ATLAS Upgrade Workshop Upgrade of the Tile. CAL LVPS System Gary Drake Argonne National Laboratory, USA In Collaboration with The University of Chicago CERN Feb. 25, 2009

Outline of Talk I. III. IV. Goals for the LVPS Upgrade Current Plans & Thinking Primary Issues, Critical Decisions, Required R&D Summary Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 2

General System Guidelines and Goals for the LVPS System 1. Primary Motivation: Improve radiation hardness of electronics ð 2. LVPS bricks must be replaced for s. LHC environment… Improve Reliability a. Connectors i. ii. b. Reduce number of connections & interconnects Improve reliability and robustness of connectors Implement redundancy to prevent single-point failures 3. Generally reduce complexity of system where possible 4. Reduce numbers of voltages to be generated 5. Eliminate sensitivities to IR drops 1. Eliminate need for tight regulation by LVPS n Use “point-of-load” regulators CERN rad-hard regulators Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 3

The Current LVPS System n Present System Architecture – 2 -Stage System Mother Boards Local CKTs 14 LVPS To Other Drawers Digitizers Local CKTs On Detector 1 per Drawer On Detector 1 per 4 Drawers 200 VDC Splitter Box FE Circuitry In Drawer +3 DIG, +5 DIG, -5 MB, +15 MB, -15 HV, +5 HV And Returns 4 USA 15 200 VDC Bulk 200 VDC Stage 2 Digitizers Local CKTs 4 To Other Splitter Boxes HV Dist. System Local CKTs 6 Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN Stage 1 4

The Current LVPS System splitter box n Tile. CAL LVPS System – 2 -stage system Custom LVPS Boxes One per Drawer 256 Total 200 V dc in, 3 V, 5 V, 15 V Out USA 15 200 V dc BULK SUPPLY 3 f 240 VAC 200 V dc Main Barrel side 70 m long cable Extended Barrel sides 100 m long cable Commercial 24 HPS 1 Units Each powers 12 f. LVPS Graphic by I. Hruska, B. Palan Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 5

The Current LVPS System n Current f. LVPS configuration Power Daisy Chain HV Capton Foil HV control and distribution board 6 Power daisy chain 12 LVPS 14 Motherboard Digitizer pmt 3 in 1 Harting connector 6 8 Motherboard 4 4 4 Digitizer 4 Motherboard 4 4 Digitizer data to ROD optical Interface 4 4 Digitizer 100 TTC Motherboard Flex Foils (data, TTC ) BUS Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN Graphic by G. Usai, UC 6

The Current LVPS System n Current Configuration of LVPS Box 72 pin Harting Connector LVPS Box 8 Bricks/Box +3 DIG & Returns +5 MB & Returns -5 MB & Returns +15 MB & Returns +5 HV & Returns -15 HV & Returns +15 HV & Returns 4 +3 DIG Brick 4 +5 DIG Brick 8 +5 MB Brick 4 -5 MB Brick 2 +15 MB Brick 2 +5 HV Brick 2 -15 HV Brick 2 200 V Dist. Board 200 VDC 6 Ground 6 ELMB Mother Board CAN Bus 10 +15 HV Brick Range of Voltages: 5: 1 Range of Currents: 62: 1 ð One Basic Brick Design Different Component Values Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 7

The Proposed New Power Distribution System n New System Architecture – 3 -Stage System Local CKTs POL REGs +/-10 VDC and Returns 4 (8*) On Detector 1 per Drawer LVPS On Detector 1 per 4 Drawers 200 VDC Splitter Box FE Circuitry In Drawer To Other Drawers USA 15 200 VDC Bulk 200 VDC Stage 2 Local CKTs POL REGs 4 (8*) Stage 3 To Other Splitter Boxes Stage 1 - Point-of-Load Regulators * Numbers in parentheses for implementation of redundancy Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 8

Point of Load Regulators Local CKTs POL REGs +/-10 VDC n Work is in progress at CERN to develop rad-hard DC-DC Converter to be used as local point-of-load regulators – Use one by every chip, or group of chips, depending on current demand – Primary development is for silicon tracker high radiation environment – Tile. CAL radiation environment is less demanding, so we can piggyback n Some Parameters: – – – Radiation hard DC-DC converters with air-core inductors Low drop voltage regulators in 130 nm and below DC-DC buck converter architecture Vin: +10 ~ +12 V, Vout: +1. 8 ~ +5 V, 6 W, 85 – 90% efficiency Radiation and magnetic field hard Contact persons: F. Faccio & G. Blanchot More info http: //indico. cern. ch/conference. Display. py? conf. Id=39721 ðWe will be testing prototypes as soon as they become available ð Caveat: Not working on rad-hard negative voltage regulators (yet)… Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 9

The Proposed New Power Distribution System splitter box n The New LVPS System – 3 -stage system ð Same Infrastructure Custom LVPS Boxes One per Drawer 256 Total 200 V dc in, +/- 10 V Out ð New Bricks Same Physical Size Need new boxes… USA 15 200 V dc BULK SUPPLY 3 f 240 VAC 200 V dc Main Barrel side 70 m long cable Extended Barrel sides 100 m long cable Commercial 24 HPS 1 Units Each powers 12 f. LVPS Modified from Graphic by I. Hruska, B. Palan Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 10

The Proposed New Power System n New Configuration of LVPS Box (1) or (2*) 64 pin Harting Connectors 8 Bricks/Box +10 V & Returns -10 V & Returns 200 V Dist. Board 8 (16) +10 V Brick 8 (16) -10 V Brick 8 (16) 200 VDC 6 Ground 6 Control Board Control & Monitoring GBT? -10 V Brick Range of Voltages: Range of Currents: 1: -1 1: 1 (2: 1) ð Two Brick Designs * Numbers in parentheses for implementation of redundancy Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 11

The Proposed New Power Distribution System n A possible implementation… Star distribution system: 4 (8*) HV control & distribution board GBT PMT GBT Optical To USA 15 PMT HV PMT Front End LVPS 24 (1 Drawer) PMT Front End PMT HV Front End 200 V 4 (8*) HV control & distribution board Front End PMT GBT 24 (1 Drawer) +/-10 V 4 (8*) Readout Bd Service 4 PMTs Data, Control, Readout Bd Service 4 PMTs 4 (8*) Readout Bd Service 4 PMTs & Timing Readout Bd Service 4 PMTs 4 (8*) Readout Bd Service 4 PMTs 1 Link/Board Readout Bd Service 4 PMTs 4 (8*) Readout Bd Service 4 PMTs Optical To USA 15 Readout Bd Service 4 PMTs 4 (8*) ð Each of 8 bricks in LVPS Box services 2 (4*) Readout Bds ð Nearly balanced loads! * Numbers in parentheses for implementing redundancy Modified from Graphic by G. Usai, UC Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 12

Implementing Redundancy n How to implement power supply redundancy: Diode OR Vd 2 Vs 2 – – + - Vs 1 Vd 1 PCB Vload Load Greater of (Vs 1 – Vd 1) or (Vs 2 – Vd 2) provides current to load Diodes may share if diode IV characteristics are soft, and/or if 2 paths ~match No need to bin diodes; Only moderate trim of output voltages needed On average, power supplies will each share half the total load, within window ð Power supplies on average operate at half their rated power aids in longevity ð Each power supply must be capable of providing full power though ð Technique used successfully for CDF Run 1 ð Need more experience with current system to decide if this is worth it… Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 13

Monitoring & Control n Probably will want to monitor same quantities as presently: – 8 input voltages – 8 output voltages – 8 input currents – 8 output currents – Temperatures ð The difference: only 2 sets of quantities, not 8… ð No longer need to monitor sense lines, if use POL regulators… n Control – No longer need trim control regulators are insensitive to their Vin – Will want method for turning on & off whole boxes – May want method for turning on & off individual bricks… Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 14

Primary Issues, Critical Decisions, Required R&D n Need to choose a system architecture n Need to identify and specify all components in the drawer – Identify voltages needed – Define currents needed ð Define total voltage, current, and power consumption for drawer n Point-of-Load Regulators – Based on needs, will CERN regulator be sufficient? • Obtain prototype samples; performance testing; radiation testing • Is there any circuitry that can’t operate within +/-5 V? – What to do about negative voltage regulator • CERN? • Another IC design group? • Commercial vendor? n Preliminary brick component selection – Radiation testing n Decision on implementing redundancy – Experience with current system will be a good guide… Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 15

Primary Issues, Critical Decisions, Required R&D (Cont. ) n Control & monitoring – – – ð GBT? New ELMB_MB equivalent? Custom chip development? Needs more thought & work… n Prototype brick design – Can begin early, with approximate guesses on current & power – Will need final specs to complete design • Design for factor of 2 capability if implement redundancy • Design for 80% maximum capacity on a single supply n Connector Decisions – Depends on • Architecture • Currents • Distribution of loads – Includes power connections, & all internal connections inside box ð Possibly the most important decision in the project Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 16

Summary n Advocating 3 stage power distribution system – Stage 1 – bulk 200 V in USA 15 OK – Stage 2 – LVPS boxes • • New design +/- 10 V only Tight regulation not important Advocating balanced loads – Stage 3 – Point-of-Load regulators • Relying on CERN development for positive voltage regulator • Still need to identify/develop negative voltage regulator n Primary issues needing to be addressed: – – – – System architecture Drawer electronics design voltages & currents required Point of load regulators: test CERN design; address negative voltages Component selection radiation testing Address need for redundancy Choose connectors Prototype development… Testing… FE tests… Vertical Slice Tests… Upgrade of the Tile. CAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN 17