ATLAS Tile Calorimeter Interface The 8 th Workshop

ATLAS Tile Calorimeter Interface The 8 th Workshop on Electronics for LHC Experiments, Colmar, 9 -13 September 2002 K. Anderson, A. Gupta, J. Pilcher, H. Sanders, F. Tang, R. Teuscher, H. Wu The University of Chicago Introduction Interface Design Performance and Radiation Test Results Production Quality Control Conclusions

INTRODUCTION: Tile. Cal and Its Readout Electronics & 64 modules in barrel region Ø (r 1=2. 28 M r 2=4. 23 M L=5. 64 M) & 128 modules in extended regions Ø (r 1=2. 28 M r 2=4. 23 M L= 2. 65 M) & 256 electronics drawers (64 x 4) Tile. Cal Interface

INTRODUCTION: Tile. Cal and Its Readout Electronics Each Electronics Drawer Contains Following Electronics Boards: n n 45 PMT Blocks in barrel region 31 PMT Blocks in extended regions Ø One Front-end Electronics 3 -in-1 Card Per PMT Block n n n PMT High Voltage Boards 3 -in-1 Motherboard (4 sections) 8 Trigger Summing Cards in barrel region n n 6 Trigger Summing Cards in extended region. n n (Stacked on 3 -in-1 Motherboard) 1 Source Calibration Card n n (Stacked on 3 -in-1 Motherboard) 8 Digitizer Boards in barrel region 6 Digitizer Boards in extended regions 1 Interface Card n (Stacked on one of Digitizer Boards)

INTRODUCTION: Interface Location in Electronics Drawer n A total of 256 Interface cards needed (One per drawer) n Card dimensions: 189 x 100 mm n Located near center of drawer n Receive TTC optical signals in electronics drawer for functional and timing controls q Convert to LVDS signals and distribute to 8 digitizer boards and 3 -in-1 mother board n Transfer event data from digitizer boards to RODs q Input from 8 Digitizer Boards (from 16 Tile-DMU chips) q Output to off-detector ROD modules via G-link

INTERFACE DESIGN: Goals: • Complete 2 -fold redundancy to ROD. (except for LVDS receivers) ü Avoid single point of failure for data from full drawer ü Output data robust against transient SEE errors on link • TTC failure detection and automatic switch function ü Interface automatic selects a TTC signal based on signal failure conditions

INTERFACE DESIGN: Goals (Cont. 1) Goals: • Data Organizer ü Collect data from 16 Tile- Altera EP 20 K 160 E DMUs in parallel based on Tile-DMU output protocol ü Repack 32 -bit data words from scrambled data transferred over 2 -bit LVDS data lines (40 Mpbs) ü Insensitive to timing differences related to digitizer board geometry ü CRC-16 and Global CRC transmission error checks over input and output segments

INTERFACE DESIGN: Goals (Cont. 2) Goals: • Data Organizer ü G-link protocol control logic. ü 640 Mbps output data rate (371 Mbps required for Tile. Cal @ 100 Khz LVL 1 A rate) Altera EP 20 K 160 E • Low Cost FPGA designs ü Altera EP 20 K 200 E ü On-board JTAG configuration port • Single 3. 3 V Power Supply

INTERFACE DESIGN: TTC Receiver Output Waveforms

INTERFACE DESIGN: Structure of Data Organizer

INTERFACE DESIGN: Tile-DMU data stream format

INTERFACE DESIGN: Tile-DMU data stream format

INTERFACE DESIGN: Repacked stream data format

INTERFACE DESIGN: G-link Optical Transmitter (Taiwan) max 3288 cue From G-link Serializer VCSEL Diode Serializer Output Waveforms

TEST RESULTS: System Readout Performance Muon response for the 3 sampling depths (q=90 o) v. Pedestal Superimposed • Using “signal” from empty events • Width reflects energy algorithm as well as electronics • 10 digitizations for each measurement (not optimized) Muon signal well resolved from pedestal

TEST RESULTS: Radiation Requirements ØInterface located at z=160 cm r=410 cm Radiation Type Sim. Level Safety Factors Required Level Sim. Low Lot Total Dose Varn. Rate TID 0. 023 Krd 3. 5 5 4 70 1. 6 Krd NIEL 1. 5 x 1010 n/cm 2 5 1 4 20 3. 0 x 1011 n/cm 2 SEE 6. 3 x 108 h/cm 2 5 1 4 20 1. 3 x 1010 h/cm 2

TEST RESULTS: Radiation Tests Ø Interface located at z=160 cm r=410 cm ü All 3 studies showed Interface was fully operational under tests Radiation Required Type Level Source Exposed Dose Test Lab TID 1. 6 Krd Colbt-60 2. 4 krd Argonne NIEL 3. 0 x 1011 n/cm 2 Neutron 5. 0 x 1011 n/cm 2 CEA/ PROSPERO Dijon, France SEE 1. 3 x 1010 h/cm 2 Proton 1. 5 x 1010 p/cm 2 Indiana Univ

Production Quality Control n Web Materials ü ü n n n Schematics, specification drawings, gerber, QC requirements, revision history etc. Instructions to vendor (PCB and assembly) Parts, artwork files provided by Chicago, vendor responsible for PCB fabrication and assembly 5 trial boards based on full production setup Burn-in test (power-up @65 C for one week) All functional and performance tests Record to Database (Web accessible) Others

Conclusions ü Design is well suited to our needs ü Performance and Radiation tests demonstrated well satisfactory ü Mass production is being installed in Tile. Cal