A Comprehensive Metrics Driven Methodology to Measure and

A Comprehensive Metrics Driven Methodology to Measure and Improve Soft-IP Quality Anuj Kumar - Atrenta Andy Wu - TSMC DAC 2014 - IP Track Submission

Background and Motivation Standardize IP Handoff & Acceptance Quality Checks § To define a comprehensive set of quality checks to assess the implementation readiness for soft IPs to enable a smooth IP handoff / acceptance flow. § These quality checks are derived from Atrenta’s Reference Guide. Ware 2. 0 Methodology for IP and So. C RTL Signoff and later renamed as “TSMC Soft IP Quality Golden Rules” § TSMC Soft IP Quality Checks should be equally applicable for different types of Soft IP e. g. internal, legacy, or 3 rd party RTL IPs / Blocks Enable Easy Adoption of the Flow to Benefit a Wide Variety of IP-So. C Ecosystem Partners § The IP Qualification flow should be easy to setup § Get to the meaningful (high coverage low noise) results with self guided and systematic approach Provide Portable, Easy to Read / Correlate, and Quality Metrics Objective-based Handoff / Acceptance Reports Flow Should be Scalable and Easy to Integrate in Existing Design Flow Environments DAC 2014 - IP Track Submission 2

Overview of TSMC 9000 Soft IP Qualification Program TSMC Online IP Ecosystem Partners IP supplier 1 Atrenta Dash. Board End Customers IP 1 Chip project 1 IP 2 IP supplier 2 TSMC IP Kit IP supplier 3 IP 3 Chip project 2 TSMC IP Kit Chip project 3 Handoff … IP supplier n DAC 2014 - IP Track Submission IP n Atrenta Data. Sheet Inspection / Acceptance … Chip project n 3

TSMC IP IP Handoff Kit TSMC Handoff IP TSMC IP Handoff Kit Doc, training, scripts Physical Constr Power DFT Lint CDC Guide. Ware goals IP reports waivers UPF/CPF FSDB, … SDC SGDC RTL IP Design Intent …. Quickstart Training Scripts, Guide module setup Atrenta Data. Sheet Atrenta Dash. Board Deliverables Spy. Glass Clean IP DAC 2014 - IP Track Submission 4

TSMC IP Handoff Kit – Inputs / Outputs TSMC IP Handoff Kit Project file TSMC IP Handoff Methodology Tech Libs (. lib) Std. Design Constraints Simulation Inputs (SDC, VCD/FSDB, UPF/CPF) SGDC file Spy. Glass Waiver file Other setup files RTL (. v/. sv/. vhd) IP Handoff Deliverables RTL+Tech. Libs Design Analysis/Quality Metrics Reports RTL Tech Libs CDC Fault Covg Power Data. Sheet Dash. Board moresimple count Sign_off Spy. Glass Setup Files Spy. Glass Project File (. prj) Waivers (. swl) SGDC SDC UPF/CPF VCD/FSDB/SAIF SDC Coverage DAC 2014 - IP Track Submission 5

Key Soft IP-Kit Quality Checks Ø Best practices lint checks Ø IP readiness for simulation & synthesis analysis Ø Identification of deadcode, x-assignment, unreachable states Ø Multi mode/corner/design scenarios RTL Power Estimation Ø Power Intent(UPF/CPF) verification Ø Fault/Test Coverage Analysis (Stuck@ & Transition) IP TSMC IP Kit SG-Lint SG-Advance. Lint SG-Power. Verify Ø Clock/Reset Propagation (Glitch, convergence) Analysis SG-DFT Ø Asynchronous Clock Domain Crossing Path Verification SG-Clocks Ø Timing constraints(SDC) checks for completeness & consistency Ø Verification of Timing Exceptions(FP, MCP) Ø Area, timing(negative slack paths) & congestion analysis SG-Constraints SG-Txv SG-Physical Spy. Glass Clean IP DAC 2014 - IP Track Submission 6

TSMC IP Kit Execution Flow Design Read >% aipk_read -top foo –srcfile foo. f –libfile lib. f – sdcfile foo. sdc -activity_file foo. vcd Design Setup Checks >% aipk_read –top foo Basic Design Checks >% aipk_run –top foo –goals basic_check Advanced Design Checks >% aipk_run –top foo –goals adv_check IP Packaging ü Auto-generation of Spy. Glass setup files (. prj, . sgdc, . swl, . dat , etc. ) ü Generation of Design Read Dash. Board report ü Ensures that RTL is read in successfully ü Identifies unconstrained clock/resets in the design ü Ensures that design setup is complete & correct ü Runs basic IP handoff checks (Lint, CDCStructural, DFT, SDC, Power) ü Generates quality report for basic design checks/goals ü Runs advanced IP handoff checks (CDC functional, Lint functional & physical) ü Generates overall quality report combining results for basic & advanced checks ü Packages an IP with design intent, setup & analysis reports >% aipk_pack –top foo –save_all DAC 2014 - IP Track Submission 7

Soft IP Quality Metrics Dash. Board Report DAC 2014 - IP Track Submission 8

IP Specification/Datasheet Report TSMC IP Kit generates the Spy. Glass Data. Sheet report capturing key design specifications and profile statistics, once all goals run are finished Design Read DAC 2014 - IP Track Submission Design Setup Check Design Analysis IP Packaging 9

Sample Results from TSMC IP Kit Analysis IPStats Test Power % ports constrained % registers constrained No. of unverified FP No. of unverified MCP Internal (m. W) Leakage (u. W) Switching (m. W) 462 130 22 98 46637 36 212 88 8907 22027 40626 99 2537 275 757 100 9000 4279 1387 100 4806 2552 3802 99 94023 12 47 98 59125 121 65 99 4546 1300 523 99. 7 SDC Test Coverage(transition@) Test Coverage(stuck@) Synchronized CDCs Unsynchronized CDCs 8817 2154640 227585 23000 39000 47000 489245 210201 20125 Flop Count 21885 8668514 639021 57000 95000 110000 2201603 907303 70439 Instance Count Gate Count Core-1 Vendor A Vendor B Vendor C -IP 1 Vendor C-IP 2 Vendor C-IP 3 Vendor D-IP 1 Vendor D-IP 2 Vendor E-IP 1 … CDC 94. 3 85. 3 92. 3 98. 7 91. 2 94. 1 91. 8 91 94. 9 98 65 81 98 89 99 99 100 100 100 99 100 100 0 0 0 2 0 0 0 2 0 8 4 65 23 11 40 12 118 117 9. 46 72. 9 350 2880 13. 9 21. 7 24. 2 1870 8140 64. 2 2. 3 79 15 4. 9 65 12 115 20 0. 95 30+ Soft IPs qualified from 20 different IP vendors enrolled in the TSMC Soft IP 9000 Program so far…. DAC 2014 - IP Track Submission 10

TSMC IP Kit – A Typical User Adoption Flow IP 1 Legacy IP STANDARDIZED IP INSPECTION IP 1 Legacy IP blocks IP 1 New RTL blocks IP 1 3 rd party IP IP Suppliers TSMC IP Kit IP 1 RTL New IP 1 3 rd party IP blocks Atrenta Data. Sheet Atrenta Dash. Board + IP design intent HIGH QUALITY IP BLK 1 BLK 2 So. C Integrators BLK 3 SMOOTH So. C INTEGRATION DAC 2014 - IP Track Submission BLK n So. C MINIMIZE ITERATIONS 11

TSMC IP Kit – User Benefits Standardized inspection flow for all IPs including ones from internal sources (new, legacy, older designs) Propagate IP design intent – SDC/SGDC, waivers, *PF, … for chip integration Beyond functional verification… Maximize internal IP re-use IP integrates efficiently Fully verified IP Automated regression flow runs the IP kit nightly and generates Data. Sheet & Dash. Board reports Automatically track IP updates/ bug fixes DAC 2014 - IP Track Submission Verify IP for CDC, SDC, DFT, *PF, … Review Data. Sheet and Dash. Board to select the correct IP Create an IP repository with published reports IP selection based on objective quality & spec metrics Streamline IP delivery and track usage 12

Summary / Conclusion Spy. Glass, TSMC Soft IP Quality Golden/Guide. Ware Rules and Atrenta Design analysis reports(Dash. Board/Data. Sheet) together provide a comprehensive, detailed and design objective based Soft-IP quality assessment report. TSMC and Atrenta have partnered to adapt these tools for TSMC’s soft IP 9000 Qualification Program. A comprehensive set of quality checks, as included in TSMC IP Kit, has been defined and documented in Design Metric Reports. TSMC IP Kit Flow successfully adopted by 20+ IP ecosystem partners, which was quite helpful in improving the implementation readiness for their various Soft-IPs. Summary results of IPs for IP ecosystem partners are posted on TSMC Online DAC 2014 - IP Track Submission 13